scholarly journals Efficient FPGA-Based Architecture of the Overlap-Add Method for Short-Time Fourier Analysis/Synthesis

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1533 ◽  
Author(s):  
Mohammed Bahoura
Keyword(s):  
Fourier Analysis ◽  
Field Programmable Gate Array ◽  
Original Signal ◽  
Programming Tool ◽  
Objective Metrics ◽  
Field Programmable ◽  
Signal Processing Algorithms ◽  
Processing Algorithms ◽  
High Level ◽  
Short Time

This paper proposes a simple and efficient FPGA-based architecture of the overlapping/windowing and overlap-add methods for real-time FFT/IFFT-based signal processing algorithms. The analyzed signal is divided into short-time overlapping frames that are windowed before applying Fourier analysis/synthesis. Then, the original signal is reconstructed from the windowed (modified) frames using the overlap-add (OLA) technique. The proposed architecture was implemented on Field Programmable Gate Array (FPGA) using a high-level programming tool in MATLAB/SIMULINK environment. Its performance was evaluated on artificial and actual signals using objective metrics.

scholarly journals A Programmable Receiver for Communication Systems and Its Application to Impulse Radio

2009 ◽  
Vol 2009 ◽  
pp. 1-5 ◽  
Author(s):  
Roman Merz ◽  
Cyril Botteron ◽  
Frédéric Chastellain ◽  
Pierre-André Farine
Keyword(s):  
Field Programmable Gate Array ◽  
Communication Systems ◽  
Indoor Environment ◽  
Impulse Radio ◽  
Ultra Wideband ◽  
System Architectures ◽  
Analog To Digital ◽  
Field Programmable ◽  
Signal Processing Algorithms ◽  
Processing Algorithms

The design of a programmable receiver for an ultra wideband (UWB) communication is presented. The receiver is using a fast analog to digital converter (ADC) and a field programmable gate array (FPGA) allowing a rapid performance evaluation for various system architectures and signal processing algorithms. To demonstrate the performance and the versatility of the receiver, a simple communication system and a localization system are implemented. The accuracy of the latter is presented for an indoor environment.

scholarly journals Smart sensing metasurface with self-defined functions in dual polarizations

Nanophotonics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 3271-3278 ◽  
Author(s):  
Qian Ma ◽  
Qiao Ru Hong ◽  
Xin Xin Gao ◽  
Hong Bo Jing ◽  
Che Liu ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
The Other ◽  
Rf Power ◽  
Pin Diodes ◽  
Self Recognition ◽  
Field Programmable ◽  
Power Detector ◽  
Smart Sensing ◽  
High Level ◽  
Rf Power Detector

AbstractFor the intelligence of metamaterials, the -sensing mechanism and programmable reaction units are two important components for self-recognition and -determination. However, their realization still face great challenges. Here, we propose a smart sensing metasurface to achieve self-defined functions in the framework of digital coding metamaterials. A sensing unit that can simultaneously process the sensing channel and realize phase-programmable capability is designed by integrating radio frequency (RF) power detector and PIN diodes. Four sensing units distributed on the metasurface aperture can detect the microwave incidences in the x- and y-polarizations, while the other elements can modulate the reflected phase patterns under the control of a field programmable gate array (FPGA). To validate the performance, three schemes containing six coding patterns are presented and simulated, after which two of them are measured, showing good agreements with designs. We envision that this work may motivate studies on smart metamaterials with high-level recognition and manipulation.

scholarly journals Stepwise Transformation of Algorithms into Array Processor Architectures by the DECOMP

VLSI Design ◽  
1995 ◽  
Vol 3 (1) ◽  
pp. 67-80
Author(s):  
Uwe Vehlies
Keyword(s):  
Digital Signal ◽  
Design Flow ◽  
Array Processor ◽  
Formal Approach ◽  
Processor Architectures ◽  
Massively Parallel Systems ◽  
Signal Processing Algorithms ◽  
Hardware Description ◽  
High Level ◽  
Short Time

A formal approach for the transformation of computation intensive digital signal processing algorithms into suitable array processor architectures is presented. It covers the complete design flow from algorithmic specifications in a high-level programming language to architecture descriptions in a hardware description language. The transformation itself is divided into manageable design steps and implemented in the CAD-tool DECOMP which allows the exploration of different architectures in a short time. With the presented approach data independent algorithms can be mapped onto array processor architectures. To allow this, a known mapping methodology for array processor design is extended to handle inhomogeneous dependence graphs with nonregular data dependences. The implementation of the formal approach in the DECOMP is an important step towards design automation for massively parallel systems.

AN EVOLUTIONARY ALGORITHM FOR THE ALLOCATION PROBLEM IN HIGH-LEVEL SYNTHESIS

2005 ◽  
Vol 14 (02) ◽  
pp. 347-366 ◽  
Author(s):  
HAIDAR M. HARMANANI ◽  
RONY SALIBA
Keyword(s):  
Evolutionary Algorithm ◽  
Allocation Problem ◽  
High Level Synthesis ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Functional Units ◽  
High Level ◽  
The Cost ◽  
Short Time

This paper presents an evolutionary algorithm to solve the datapath allocation problem in high-level synthesis. The method performs allocation of functional units, registers, and multiplexers in addition to controller synthesis with the objective of minimizing the cost of hardware resources. The system handles multicycle functional units as well as structural pipelining. The proposed method was implemented using C++ on a Linux workstation. We tested our method on a set of high-level synthesis benchmarks, all yielding good solutions in a short time. An integration path to Field Programmable Gate Arrays (FPGAs) is provided through VHDL.

High Level Transformation Techniques for Designing Reliable and Secure DSP Architectures

2020 ◽  
pp. 164-174
Author(s):  
Jyotirmoy Pathak ◽  
Abhishek Kumar ◽  
Suman Lata Tripathi
Keyword(s):  
Signal Processing ◽  
Reverse Engineering ◽  
Real Time ◽  
Time Signal ◽  
Transformation Techniques ◽  
Signal Processing Algorithms ◽  
Processing Algorithms ◽  
High Level ◽  
Real Time Signal Processing

Reverse engineering (RE) has become a serious threat to the silicon industry. To overcome this threat, the ICs need to be made secure and non-obvious in order to find their functionality with their architecture. Real-time signal processing algorithms need to be faster and more reliable. Adding up additional circuits for increasing the security of the IC is not permittable due to increase in overhead of the IC. In this chapter, the authors introduce a few high-level transformations (HLT) that are used to make the circuit more reliable and secure against the reverse engineering without having overhead on the IC.

A Gracefully Degrading and Energy-Efficient FPGA Programming using LabVIEW

2016 ◽  
Vol 5 (3) ◽  
pp. 165
Author(s):  
B. Naresh Kumar Reddy ◽  
N. Suresh ◽  
J.V.N. Ramesh
Keyword(s):  
Complex Signal ◽  
Graphical Language ◽  
Gate Arrays ◽  
Signal Flow Graphs ◽  
Field Programmable ◽  
Signal Processing Algorithms ◽  
Programmable Gate Arrays ◽  
Labview Fpga ◽  
High Level ◽  
Flow Graphs

<p>Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise. FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.</p>

scholarly journals Hardware Considerations for Tensor Implementation and Analysis Using the Field Programmable Gate Array

Electronics ◽  
2018 ◽  
Vol 7 (11) ◽  
pp. 320 ◽  
Author(s):  
Ian Grout ◽  
Lenore Mullin
Keyword(s):  
Machine Learning ◽  
Field Programmable Gate Array ◽  
Digital Signal ◽  
Learning Systems ◽  
Complex Data ◽  
Outer Product ◽  
Typical Application ◽  
Field Programmable ◽  
Processing Algorithms ◽  
Gate Array

In today’s complex embedded systems targeting internet of things (IoT) applications, there is a greater need for embedded digital signal processing algorithms that can effectively and efficiently process complex data sets. A typical application considered is for use in supervised and unsupervised machine learning systems. With the move towards lower power, portable, and embedded hardware-software platforms that meet the current and future needs for such applications, there is a requirement on the design and development communities to consider different approaches to design realization and implementation. Typical approaches are based on software programmed processors that run the required algorithms on a software operating system. Whilst such approaches are well supported, they can lead to solutions that are not necessarily optimized for a particular problem. A consideration of different approaches to realize a working system is therefore required, and hardware based designs rather than software based designs can provide performance benefits in terms of power consumption and processing speed. In this paper, consideration is given to utilizing the field programmable gate array (FPGA) to implement a combined inner and outer product algorithm in hardware that utilizes the available hardware resources within the FPGA. These products form the basis of tensor analysis operations that underlie the data processing algorithms in many machine learning systems.

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