scholarly journals A Ruggedness Improved Mobile Radio Frequency Power Amplifier Module with Dynamic Impedance Correction by Software Defined Atomization

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1317 ◽  
Author(s):  
Jooyoung Jeon ◽  
Myounggon Kang
Keyword(s):  
Radio Frequency ◽  
Power Amplifier ◽  
Bias Voltage ◽  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Impedance Change ◽  
Load Impedance ◽  
Power Added Efficiency

A ruggedness improved multi-band radio frequency (RF) power amplifier (PA) module applicable to mobile handsets, which are required to survive against a serious load impedance change under extreme power and bias conditions, is presented. In this method, the load impedance of PA is adaptively adjusted with a digitally controlled impedance corrector to keep the PA safe by performing a load mismatch detection. The impedance mismatch detector, impedance corrector, and other RF switches were all integrated into a single integrated circuit (IC) using silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS). For the verification purpose, a 2-stage hetero junction bipolar transistor (HBT) PA module adopting this method was fabricated. At a frequency of 1915 MHz, a collector bias voltage of 4.2 V, and over a wider range of load impedance variation between a VSWR of 1 and a VSWR of 5.5, it did not fail. When this technique was not applied with a voltage standing wave ratio (VSWR) range of 1 to 4, it resulted in an acceptable RF performance degradation of 1% power added efficiency (PAE) in envelope tracking (ET) mode. Moreover, it survived at a bias voltage 1V larger than when the technique was not applied for the same mismatch condition.

scholarly journals Ka-Band Stacked Power Amplifier Supporting 3GPP New Radio FR2 Band n258 Implemented Using 45 nm CMOS SOI

2021 ◽  
Vol 11 (15) ◽  
pp. 6708
Author(s):  
Janne P. Aikio ◽  
Alok Sethi ◽  
Mikko Hietanen ◽  
Jere Rusanen ◽  
Timo Rahkonen ◽  
...  
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Error Vector Magnitude ◽  
Fully Integrated ◽  
Power Added Efficiency ◽  
Wireless Applications ◽  
Ofdm Signal ◽  
New Radio

This paper presents a fully integrated, four-stack, single-ended, single stage power amplifier (PA) for millimeter-wave (mmWave) wireless applications that was fabricated and designed using 45 nm complementary metal oxide semiconductor silicon on insulator (CMOS SOI) technology. The frequency of operation is from 20 GHz to 30 GHz, with 13.7 dB of maximum gain. The maximum RF (radio frequency) output power (Pout), power-added efficiency (PAE) and output 1 dB compression point are 20.5 dBm, 29% and 18.8 dBm, respectively, achieved at 24 GHz. The error vector magnitude (EVM) of 12.5% was measured at an average channel power of 14.5 dBm at the center of the the 3GPP/NR (third generation partnership project/new radio) FR2 band n258—i.e., 26 GHz—using a 100 MHz 16-quadrature amplitude modulation (QAM) 3GPP/NR orthogonal frequency division modulation (OFDM) signal.

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

A 60 GHz 14 dBm power amplifier with a transformer-based power combiner in 65 nm CMOS

2011 ◽  
Vol 3 (2) ◽  
pp. 99-105 ◽  
Author(s):  
Dixian Zhao ◽  
Ying He ◽  
Lianming Li ◽  
Dieter Joos ◽  
Wim Philibert ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Peak Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
60 Ghz ◽  
Power Combiner ◽  
Power Added Efficiency ◽  
Saturated Output Power

A 52–61 GHz power amplifier (PA) is implemented in 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The proposed PA employs a transformer-based power combiner to sum the output power from two unit PAs. Each unit PA uses transformer-coupled two-stage differential cascode topology. The differential cascode PA is able to increase the output power and ensure stability. The transformer-based passives enable a compact layout with the PA core area of only 0.3 mm2. The PA achieves a peak power gain of 10.2 dB with 3-dB bandwidth of 9 GHz. The measured saturated output power is 14.8 dBm with a peak power-added efficiency (PAE) of 7.2%. The reverse isolation is smaller than −33 dB from 25 to 65 GHz. The PA consumes a quiescent current of 143 mA from a 1.6 V supply.

MMIC-based asymmetric Doherty power amplifier for small cells applications

2014 ◽  
Vol 7 (5) ◽  
pp. 499-505 ◽  
Author(s):  
Xavier Moronval ◽  
Reza Abdoelgafoer ◽  
Adeline Déchansiaud
Keyword(s):  
Power Amplifier ◽  
Integrated Circuit ◽  
Oxide Semiconductor ◽  
System Level ◽  
Small Cells ◽  
Personal Communications ◽  
Monolithic Microwave Integrated Circuit ◽  
Power Added Efficiency ◽  
Digital Cellular ◽  
Multi Mode

We present the results obtained on a multi-mode multi-band 20 W Monolithic Microwave Integrated Circuit (MMIC) power amplifier. The proposed two-stage circuit is based on the silicon Laterally Diffused Metal Oxide Semiconductor (LDMOS) technology. Thanks to dedicated design techniques, it can cover the Digital Cellular Service (DCS), Personal Communications Service (PCS), and UMTS bands (ranging from 1.805 to 2.17 GHz) and deliver more than 20 W of output power, 30 dB of gain and 50% of power added efficiency. When combined in a Doherty configuration with an incremental 40 W MMIC in a dual-path package, the resulted asymmetric MMIC (an industry first) can deliver an unprecedented LDMOS MMIC efficiency of up to 44% at 8 dB back-off in the UMTS band. Then, the DPA has been optimized in conjunction with a novel RF pre-distortion technique, leading to 33–80% energy saving at the system level.

scholarly journals A 28 GHz Linear Power Amplifier Based on CPW Matching Networks with Series-Connected DC-Blocking Capacitors

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 617 ◽  
Author(s):  
Qingzhen Xia ◽  
Dongze Li ◽  
Jiawei Huang ◽  
Jinwei Li ◽  
Hudong Chang ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Phased Array ◽  
Continuous Wave ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Error Vector Magnitude ◽  
Output Stage ◽  
Power Added Efficiency ◽  
Matching Networks

In this paper, the influence of the DC-blocking capacitors leveraged in coplanar waveguide (CPW) matching networks is studied. CPW matching networks with series-connected DC-blocking capacitors are less sensitive to capacitance and are adopted in a 28 GHz power amplifier (PA). The PA targeting fifth-generation (5G) phased array is developed in 90 nm silicon-on-insulator complementary-metal-oxide-semiconductor (SOI CMOS) technology. A stacked field-effect-transistor (FET) architecture is elected in the output stage to boost the output power and reduce the die area. The PA with a core area of 0.31 mm2 demonstrates a maximum small signal gain of 13.7 dB and a −3 dB bandwidth of 6.3 GHz (22.9–29.2 GHz). The PA achieves a measured saturated output power (Psat) of 14.4 dBm and a peak power added efficiency (PAE) of 25% for continuous wave signals. At 24/25.6/28 GHz, the PA achieves +7.87/+9.16/+10.7 dBm measured output power and 6.21%/8.11%/10.17% PAE at −25 dBc error vector magnitude(EVM) for a 250 MHz-wide 64-quadrature amplitude modulation (64-QAM). The developed linear PA provides a great potential for low-cost 5G phased array transceivers.

scholarly journals Digitally-Controlled Bondwire Inductor with High Quality Factor and Wide Tuning Range

2020 ◽  
Vol 20 (3) ◽  
pp. 207-212
Author(s):  
Yonggoo Lee ◽  
Bomson Lee
Keyword(s):  
Quality Factor ◽  
Integrated Circuit ◽  
Tuning Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
High Quality Factor ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Wide Tuning Range ◽  
High Quality

A tunable bondwire inductor (TBI) with high-quality factor and wide tuning range is presented. The proposed TBI is fabricated on a single chip by combining a single-pole four-throw (SP4T) switch integrated circuit (IC) and four bondwire inductors on a package substrate. The SP4T switch IC is fabricated using 180 nm silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. The fabricated TBI chip exhibits a 521% tuning range of inductance from 1.77 to 11 nH at 0.1 GHz and a relatively high-quality factor. To the knowledge of the authors, the results of this work demonstrate the best combined performance of inductance tuning range and quality factor.

A 23.3 dBm CMOS power amplifier with third-order gm cancellation linearization technique achieving OIP3 of 34 dBm

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Selvakumar Mariappan ◽  
Jagadheswaran Rajendran ◽  
Norlaili Mohd Noh ◽  
Yusman Yusof ◽  
Narendra Kumar
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Continuous Wave ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Third Order ◽  
Content Type ◽  
Power Added Efficiency ◽  
Driver Amplifier ◽  
Continuous Wave Signal

Purpose The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of an long term evolution (LTE) signal with minimum trade-off to power added efficiency (PAE). Design/methodology/approach The CMOS PA is designed in a cascaded dual-stage configuration comprises a driver amplifier and a main PA. The gate voltage (VGS) of the driver amplifier is tuned to optimize its positive third-order transconductance (gm3) to be canceled with the main PA’s fixed negative gm3. The gm3 cancellation between these stages mitigates the third-order intermodulation product (IMD3) that contributes to enhanced linearity. Findings For driver’s VGS of 0.82 V with continuous wave signal, the proposed PA achieved a power gain of 14.5 dB with a peak PAE of 31.8% and a saturated output power of 23.3 dBm at 2.45 GHz. A maximum third-order output intercept point of 34 dBm is achieved at 20.2 dBm output power with a corresponding IMD3 of −33.4 dBc. When tested with a 20 MHz LTE signal, the PA delivers 19 dBm maximum linear output power for an adjacent channel leakage ratio specification of −30 dBc. Originality/value In this study, a novel cascaded gm3 cancellation technique has been implemented to achieve a maximum linear output power under modulated signals.

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