scholarly journals A Design Methodology and Analysis for Transformer-Based Class-E Power Amplifier

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 494 ◽  
Author(s):  
Alfred Lim ◽  
Aaron Tan ◽  
Zhi-Hui Kong ◽  
Kaixue Ma
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Design Methodology ◽  
Design Procedure ◽  
Cmos Process ◽  
Process Technology ◽  
Power Added Efficiency ◽  
Optimum Operation ◽  
Load Network ◽  
Class E

This paper proposes a new technique and design methodology on a transformer-based Class-E complementary metal-oxide-semiconductor (CMOS) power amplifier (PA) with only one transformer and two capacitors in the load network. An analysis of this amplifier is presented together with an accurate and simple design procedure. The experimental results are in good agreement with the theoretical analysis. The following performance parameters are determined for optimum operation: The current and voltage waveform, the peak value of drain current and drain-to-source voltage, the output power, the efficiency and the component values of the load network are determined to be essential for optimum operation. The measured drain efficiency (DE) and power-added efficiency (PAE) is over 70% with 10-dBm output power at 2.4 GHz, using a 65 nm CMOS process technology.

A 2.4-GHz 0.18μm Full-CMOS Single-Stage Class-E Power Amplifier With Temperature Effect for ISM Band Wireless Communication

2007 ◽  
Author(s):  
Mu-Chun Wang ◽  
Zhen-Ying Hsieh ◽  
Chieu-Ying Hsu ◽  
Shuang-Yuan Chen ◽  
Heng-Sheng Huang
Keyword(s):  
Temperature Effect ◽  
Output Power ◽  
Power Amplifier ◽  
Single Stage ◽  
Design System ◽  
Cmos Process ◽  
Power Added Efficiency ◽  
Ism Band ◽  
Stage Class ◽  
Class E

In this paper, we present a single-stage class-E power amplifier with multiple-gated shape as well as 0.18μm complementary metal-oxide-semiconductor (CMOS) process for 2.4GHz Industry-Science-Medicine (ISM) band. This power amplifier is able to be easily integrated into the system-on-chip (SoC) circuit. For the competition of lower cost and high integration in marketing concern, CMOS technology is fundamentally better than GaAs technology. We adopt the Advanced Design System software in circuit simulation coming from Agilent Company through the Chip Implementation Center (CIC) channel plus TSMC 0.18 μm device models. The simulation results with temperature effect, show the good performance such as an output power achievement of +22dBm under a 1.8V supply voltage; the power-added efficiency (PAE) is over 30%; the output impedance (S22) and the input impedance (S11) are fully lower than −15dB; the power gain (S21) is +11dB; the inverse isolation (S12) is below −26dB. This amplifier reaches its 1-dB compression point at an output level of 16.5dBm related to the input power 6.5dBm position. The output power with temperature variation from 0°C to 125°C depicts an acceptable spec. range, too.

scholarly journals A Modified Design of Class-E Power Amplifier with Balanced FETs and High Output Power for RFID Applications

2021 ◽  
Vol 19 ◽  
pp. 28-37
Author(s):  
Muhammad Noaman Zahid ◽  
Jianliang Jiang ◽  
Heng Lu ◽  
Hengli Zhang
Keyword(s):  
Radio Frequency ◽  
Output Power ◽  
Power Amplifier ◽  
Radio Frequency Identification ◽  
Field Effect Transistors ◽  
High Output Power ◽  
Matching Network ◽  
Power Added Efficiency ◽  
High Output ◽  
Class E

In Radio Frequency (RF) communication, a Power Amplifier (PA) is used to amplify the signal at the required power level with less utilization of Direct Current (DC) power. The main characteristic of class-E PA is sturdy nonlinearity due to the switching mode action. In this study, a modified design of class-E PA with balanced Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and high output power for Electronic Article Surveillance (EAS) Radio Frequency Identification (RFID) application is presented. MOSFETs are adjusted to have high output performance of about 80% for RFID-based EAS system. A matching network is also proposed for accurate matching because there are differences in the behavior between RF waves and low frequency waves. The design of a matching network is a tradeoff among the complexity, adjustability, implementation, and bandwidth for the required output power and frequency. The implemented PA is capable of providing 44.8 dBm output power with Power-Added Efficiency (PAE) of 78.5% at 7.7 MHz to 8.7 MHz.

scholarly journals Analysis and Compensation of the AM-AM and AM-PM Distortion for CMOS Cascode Class-E Power Amplifier

2009 ◽  
Vol 2009 ◽  
pp. 1-9 ◽  
Author(s):  
Wen An Tsou ◽  
Wen Shen Wuen ◽  
Tzu Yi Yang ◽  
Kuei Ann Wen
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Signal Source ◽  
Nonlinear Capacitance ◽  
Power Added Efficiency ◽  
Equivalent Impedance ◽  
Common Gate ◽  
Class E

Analysis and compensation methodology of the AM-AM and AM-PM distortion of cascode class-E power amplifiers are presented. A physical-based model is proposed to illustrate that the nonlinear capacitance and transconductance cause the AM-AM and AM-PM distortion when modulating the supply voltage of the PA. A novel methodology that can reduce the distortion is also proposed. By degenerating common-gate transistor into a resistor, the constant equivalent impedance is obtained so that the AM-AM and AM-PM distortion is compensated. An experimental prototype of 2.6 GHz cascode class-E power amplifier with the AM-AM and AM-PM compensation has been integrated in a 0.18 μm CMOS technology, occupies a total die area of 1.6 mm2. It achieves a drain efficiency of 17.8% and a power-added efficiency of 16.6% while delivering 12 dBm of linear output power and drawing 31 mA from a 1.8 V supply. Finally, a co-simulation result demonstrated that, when the distortion of the PA has been compensated, the EVM is improved from −17 dB to −19 dB with an IEEE802.11a-like signal source.

Performance study of an inverse class E power amplifier with series tunable parallel resonant tank

2011 ◽  
Vol 3 (4) ◽  
pp. 405-413 ◽  
Author(s):  
Tao Cao ◽  
Songbai He ◽  
Fei You
Keyword(s):  
Power Amplifier ◽  
Supply Voltage ◽  
Power Gain ◽  
Performance Study ◽  
Power Added Efficiency ◽  
Optimum Operation ◽  
Good Agreement ◽  
Class E ◽  
Class F

An analysis of operation of a modified inverse class E power amplifier is presented. The proposed amplifier that has a series tunable parallel resonant tank is similar to a hybrid of class F and inverse class E. The principles and design equations required to determine the optimum operation of the amplifier are analyzed in detail. The practical circuit using LDMOS MRF21010 is shown to be able to deliver 40.02 dBm outpout power at 155 MHz. The amplifier achieves power-added efficiency (PAE) of 78.18% and drain efficiency of 78.42%, and exhibits 25.02 dB power gain when operates from a 21 V supply voltage. Comparisons of simulated and measured results are given with good agreement between them being achieved.

scholarly journals A 28GHz Power Amplifier with Analog Predistortion Linearizer in 65nm CMOS

2021 ◽  
Vol 5 (2) ◽  
pp. 5-10
Author(s):  
He Peng ◽  
Yuqing Dou
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Supply Voltage ◽  
Linearization Method ◽  
Cmos Process ◽  
Power Added Efficiency ◽  
Saturated Output Power ◽  
Gain Compensation ◽  
Predistortion Linearization ◽  
Frequency Power

This paper proposes that a radio frequency power amplifier is suitable for a 5G millimeter wave. It adopts a three-stage single-ended structure at 28GHz. An analog predistortion linearization method is used to improve the linearity of the power amplifier (PA). As a result, there is a significant improvement in power-added efficiency (PAE) and linearity is achieved. The Ka-band PA is implemented in TSMC 65nm CMOS process. At 1.2V supply voltage, the PA proposed in this paper achieves a saturated output power of 15.9dBm and a PAE of 16%. After linearization, the output power at the 1dB compression point is increased by 2dBm, with efficient gain compensation performance.

scholarly journals Design Methodology of the Class-E Power Amplifier with Finite Feed Inductance—A Tutorial Approach

2020 ◽  
Vol 10 (24) ◽  
pp. 8765
Author(s):  
Ingrid Casallas ◽  
Carlos-Ivan Paez-Rueda ◽  
Gabriel Perilla ◽  
Manuel Pérez ◽  
Arturo Fajardo
Keyword(s):  
Analytical Model ◽  
Power Amplifier ◽  
Design Methodology ◽  
High Efficiency ◽  
Design Procedure ◽  
Mathematical Tool ◽  
Design Procedures ◽  
Iterative Design ◽  
Amplifier Design ◽  
Class E

The Class-E with finite feed inductance is a high-efficiency power amplifier that generally uses complex, long, and iterative design procedures. In this paper, we detail a design methodology that is based on an analytical model of this amplifier. This methodology explores the power amplifier design by the use of a symbolic mathematical tool, which was developed in the software Maple™. This approach helps to understand the Class-E circuit topology and it offers a fast and easy design procedure without having to examine, in-depth, the model analytical equations.

scholarly journals Design of Broadband 1.9 GHz Ga as MMIC Switching Power Amplifier for PCS Communication Services

2020 ◽  
Vol 9 (1) ◽  
pp. 396-399
Keyword(s):  
Power Amplifier ◽  
High Gain ◽  
Frequency Range ◽  
Communication Services ◽  
Power Added Efficiency ◽  
Switching Power ◽  
Compensation Technique ◽  
Load Network ◽  
Stage Class ◽  
Class E

The paper presents a broadband Monolithic microwave Switching Class–E Power amplifier using 0.5μm GaAs E-pHEMT technology for PCS communications systems operating at 1900MHz.Wider bandwidth is achieved by employing reactance compensation technique in load network of the switching power amplifier. The main Power amplifier is a single stage Class-E circuit with a driver stage driving it to achieve high gain and efficiency. The modified load network using reactance compensation network results in higher power added efficiency. The paper provides simulation results of designed two-stage Class-E Power amplifier circuit results with an power output of 20dBm, power added efficiency of 80% and gain of 26dB at the centre frequency of 1.9GHz compared with various Class-E designs of 1.9 GHz using different technologies. A high linear gain is reported in the design at the frequency range of 0.8GHz to 2.2GHz.The designed circuit achieves a wider bandwidth of 1.35GHz over a frequency range of 0.8-2.2GHz.The physical layout is drawn using GaAs foundry components and EM simulation is performed

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