scholarly journals Efficient Neural Network Implementations on Parallel Embedded Platforms Applied to Real-Time Torque-Vectoring Optimization Using Predictions for Multi-Motor Electric Vehicles

Electronics ◽  
2019 ◽  
Vol 8 (2) ◽  
pp. 250 ◽  
Author(s):  
Martin Dendaluce Jahnke ◽  
Francesco Cosco ◽  
Rihards Novickis ◽  
Joshué Pérez Rastelli ◽  
Vicente Gomez-Garay

The combination of machine learning and heterogeneous embedded platforms enables new potential for developing sophisticated control concepts which are applicable to the field of vehicle dynamics and ADAS. This interdisciplinary work provides enabler solutions -ultimately implementing fast predictions using neural networks (NNs) on field programmable gate arrays (FPGAs) and graphical processing units (GPUs)- while applying them to a challenging application: Torque Vectoring on a multi-electric-motor vehicle for enhanced vehicle dynamics. The foundation motivating this work is provided by discussing multiple domains of the technological context as well as the constraints related to the automotive field, which contrast with the attractiveness of exploiting the capabilities of new embedded platforms to apply advanced control algorithms for complex control problems. In this particular case we target enhanced vehicle dynamics on a multi-motor electric vehicle benefiting from the greater degrees of freedom and controllability offered by such powertrains. Considering the constraints of the application and the implications of the selected multivariable optimization challenge, we propose a NN to provide batch predictions for real-time optimization. This leads to the major contribution of this work: efficient NN implementations on two intrinsically parallel embedded platforms, a GPU and a FPGA, following an analysis of theoretical and practical implications of their different operating paradigms, in order to efficiently harness their computing potential while gaining insight into their peculiarities. The achieved results exceed the expectations and additionally provide a representative illustration of the strengths and weaknesses of each kind of platform. Consequently, having shown the applicability of the proposed solutions, this work contributes valuable enablers also for further developments following similar fundamental principles.

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 866 ◽  
Author(s):  
Heoncheol Lee ◽  
Kipyo Kim

This paper addresses the real-time optimization problem to find the most efficient and reliable message chain structure in data communications based on half-duplex command–response protocols such as MIL-STD-1553B communication systems. This paper proposes a real-time Monte Carlo optimization method implemented on field programmable gate arrays (FPGA) which can not only be conducted very quickly but also avoid the conflicts with other tasks on a central processing unit (CPU). Evaluation results showed that the proposed method can consistently find the optimal message chain structure within a quite small and deterministic time, which was much faster than the conventional Monte Carlo optimization method on a CPU.


2011 ◽  
Author(s):  
Zach Olson

Optical coherence tomography (OCT) techniques have opened up a number of new medical imaging applications in research and clinical applications. Key application areas include cancer research, vascular applications such as imaging arterial plaque, and ophthalmology applications such as pre and post-operative cataract surgery imaging. Emerging Technologies in galvo control, light sources, detector technologies, and parallel hardware-based processing are increasing the quality and performance of images, as well as reducing the cost and footprint of OCT systems. The parallel computing capabilities of field programmable gate arrays (FPGAs), multi-core processors, and graphics processing units (GPUs) have enabled real-time OCT image processing, which provides real-time image data to support surgical procedures.


2007 ◽  
Vol 16 (06) ◽  
pp. 997-1010
Author(s):  
AHMED A. ELFARAG ◽  
HATEM M. El-BOGHDADI ◽  
SAMIR I. SHAHEEN

Partially reconfigurable field-programmable gate arrays (FPGAs) allow parts of the chip to be configured at runtime where each part could hold an independent task. Online placement of these tasks result in area fragmentation leading to poor utilization of chip resources. In this paper, we propose a new metric for measuring area fragmentation. The new fragmentation metric gives an indication to the continuity of the occupied (or free) space and not the amount of occupied space. We show how this metric can be extended for multidimensional structures. We also show how this metric can be computed efficiently at runtime. Next, we use this measure during online placement of tasks on FPGAs, such that the chip fragmentation is reduced. Our results show improvement of chip utilization when using this fragmentation aware placement method over other placement methods with well-known bottom left, first fit, and best-fit placement strategies. In real-time environment, we achieve an improvement in miss ratio when using the fragmentation-aware placement over the bottom left placement strategy.


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