scholarly journals High-Linearity Self-Biased CMOS Current Buffer

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 423
Author(s):  
Javier Martínez-Nieto ◽  
María Sanz-Pascual ◽  
Nicolás Medrano-Marqués ◽  
Belén Calvo-López ◽  
Arturo Sarmiento-Reyes
Keyword(s):  
High Performance ◽  
Simple Structure ◽  
Low Voltage ◽  
Harmonic Distortion ◽  
Input Resistance ◽  
Cmos Process ◽  
Output Current ◽  
Current Ratio ◽  
Class Ab ◽  
Static Power

A highly linear fully self-biased class AB current buffer designed in a standard 0.18 μ m CMOS process with 1.8 V power supply is presented in this paper. It is a simple structure that, with a static power consumption of 48 μ W, features an input resistance as low as 89 Ω , high accuracy in the input–output current ratio and total harmonic distortion (THD) figures lower than −60 dB at 30 μ A amplitude signal and 1 kHz frequency. Robustness was proved through Monte Carlo and corner simulations, and finally validated through experimental measurements, showing that the proposed configuration is a suitable choice for high performance low voltage low power applications.

A Minimum-Voltage Driving Amplifier with Adaptive Three-Stage Open-Loop Gain and Folded Cascade Class-AB Output Current Control

2020 ◽  
pp. 2150145
Author(s):  
Fanyang Li ◽  
Tao Yang
Keyword(s):  
Supply Voltage ◽  
Harmonic Distortion ◽  
Open Loop ◽  
Current Control ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Loop Gain ◽  
Output Current ◽  
Class Ab ◽  
Sinusoidal Input

A driving amplifier capable of operating at a minimum voltage is proposed, aiming to subdue the distortion effect caused by large amplitude driving at the hearing aid loudspeaker. Since the linearity of a cascode amplifier usually degrades with the reduced supply voltage, a three-stage cascade amplifier having a parallel cascade second stage, and a folded cascade Class-AB output current control in place are designed. With such an arrangement, the open loop gain should still be maintained at a sufficiently high level even in the presence of increased output amplitude. Also, the minimum supply voltage required can then be reduced to merely [Formula: see text]. Fabricated on a 0.18[Formula: see text][Formula: see text]m complementary metal oxide semiconductor (CMOS) process, the proposed amplifier achieves [Formula: see text][Formula: see text]dB total harmonic distortion [Formula: see text] with a loudspeaker load of 100[Formula: see text]ohm while operating from a 1.2[Formula: see text]V supply and being subject to a 1[Formula: see text]kHz sinusoidal input.

Design and Layout of a High-Performance PWM Control Class D Amplifiers IC Systems

2012 ◽  
Vol 203 ◽  
pp. 469-473
Author(s):  
Ruei Chang Chen ◽  
Shih Fong Lee
Keyword(s):  
Low Power ◽  
High Performance ◽  
Low Voltage ◽  
Design Flow ◽  
Total Power ◽  
Cmos Process ◽  
Low Power Circuits ◽  
Class D ◽  
Total Power Consumption ◽  
Power Circuits

This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 2.8307 mW, and the chip area size is 1.1497×1.1497 mm2. Finally, the class D chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, low-power circuits, etc.

Design of a New Low Power Fully Differential Amplifier with Settling Time Enhancement Characteristics

2015 ◽  
Vol 24 (06) ◽  
pp. 1550078 ◽  
Author(s):  
Seid Jafar Hosseinipouya ◽  
Farhad Dastadast
Keyword(s):  
High Performance ◽  
Settling Time ◽  
Cmos Process ◽  
Output Stage ◽  
Common Mode ◽  
Class Ab ◽  
Fully Differential ◽  
Op Amp ◽  
Transconductance Amplifier ◽  
Adaptive Biasing

High performance of fully differential operational transconductance amplifier is designed and implemented using a 0.18-μm CMOS process. The implemented op-amp uses common mode feedback (CMFB) circuit operating in weak inversion region which does not affect other electrical characteristics due to eliminating common mode (CM) levels automatically leading to improve CM rejection ratio (CMRR) of the amplifier significantly. Moreover, the output stage has class-AB operation so that its current can be made larger due to increasing the output current dynamically using adaptive biasing circuit. Additionally, the AC currents of the active loads have been significantly reduced using negative impedances to increase the gain of the amplifier. The results show the GBW 2.3 MHz, slew rate 2.6 V/μs and 1% settling time 150 ns with a capacitive load of 15 pF. This amplifier dissipates only 6.2 μW from a 1.2 V power supply.

scholarly journals SIGNAL-PATH-LEVEL DUAL-Vt ASSIGNMENT FOR LEAKAGE POWER REDUCTION

2006 ◽  
Vol 15 (02) ◽  
pp. 197-216 ◽  
Author(s):  
YU WANG ◽  
HUAZHONG YANG ◽  
HUI WANG
Keyword(s):  
Threshold Voltage ◽  
High Performance ◽  
Low Voltage ◽  
Power Reduction ◽  
Threshold Voltages ◽  
Fast Development ◽  
Static Power ◽  
Signal Path ◽  
Subcircuit Extraction ◽  
New Algorithms

Along with the fast development of dual-threshold voltage (dual-Vt) and multi-threshold technology, it is possible to use them to reduce static power in low-voltage high-performance circuits. In this paper, we propose a new method to realize CMOS digital circuits that are implemented with dual-Vt technology. We first present a new signal-path-level circuit model which effectively deals with the fact that there can be two threshold voltages assigned to a single gate. In order to assign proper threshold voltage to all the signal-paths in the circuit, our new algorithms introduce the concept of subcircuit extraction and include the hierarchy algorithms which are effective and fast. Experimental results show that our algorithms produce a significant reduction for the ISCAS85 benchmark circuits.

A Novel Interface Circuit with 99.2% MPPT Accuracy and 1.3% THD for Energy Harvesting

2017 ◽  
Vol 26 (11) ◽  
pp. 1750176 ◽  
Author(s):  
Yani Li ◽  
Zhangming Zhu ◽  
Yintang Yang ◽  
Yadong Sun ◽  
Xu Wang
Keyword(s):  
Energy Harvesting ◽  
Conversion Efficiency ◽  
Power Efficiency ◽  
Low Voltage ◽  
Harmonic Distortion ◽  
Cmos Process ◽  
Interface Circuit ◽  
Point Tracking ◽  
Peak Output Power ◽  
Power Point

To improve conversion efficiency and output quality of the energy harvester, a novel interface circuit with composite maximum power point tracking (MPPT) in energy harvesting applications is proposed in this paper. By using the ultra-low-voltage multiplier with digital control and simple one-cycle variable frequency technique, the converter realizes fast power tracking and high conversion efficiency, and minimizes the power consumption and harmonics, thereby obtaining high tracking precise and low total harmonic distortion (THD). Implemented in 65-nm CMOS process, this converter achieves 85.9% peak power efficiency with dc output voltage of 1.6[Formula: see text]V. The peak tracking efficiency and THD are 99.2% and 1.3%, respectively. The peak output power is 18.31[Formula: see text][Formula: see text]W, and the power loss of the entire converter is only 16.53[Formula: see text][Formula: see text]W.

scholarly journals Towards Realization of a Low-Voltage Class-AB VCII with High Current Drive Capability

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2303
Author(s):  
Leila Safari ◽  
Gianluca Barile ◽  
Vincenzo Stornelli ◽  
Shahram Minaei ◽  
Giuseppe Ferri
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Current Drive ◽  
Total Power ◽  
High Signal ◽  
High Current ◽  
Class Ab ◽  
Total Power Consumption

In this paper, the implementation of a low-voltage class AB second generation voltage conveyor (VCII) with high current drive capability is presented. Simple realization and good overall performance are the main features of the proposed circuit. Proper solutions and techniques were used to achieve high signal swing and high linearity at Y, X and Z ports of VCII as well as low-voltage operation. The operation of the proposed VCII was verified through SPICE simulations based on TSMC 0.18 µm CMOS technology parameters and a supply voltage of ±0.9 V. The small signal impedance values were 973 Ω, 120 kΩ and 217 Ω at Y, X and Z ports, respectively. The maximum current at the X port was ±10 mA with maximum total harmonic distortion (THD) of 2.4% at a frequency of 1 MHz. Considering a bias current (IB) of 29 µA and output current at the X port (IX) of 10 mA, the current drive capability (IX/IB) of about 345 was achieved at the X port. The voltage swing at the Z port was (−0.4, 0.4) V. The THD value at the Z port for an input signal with 0.8 V peak-to-peak value and frequency of 1 MHz was 3.9%. The total power consumption was 0.393 µW.

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