scholarly journals Power Consumption Analysis of Bluetooth Low Energy Commercial Products and Their Implications for IoT Applications

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 386 ◽  
Author(s):  
Eduardo Garcia-Espinosa ◽  
Omar Longoria-Gandara ◽  
Ioseth Pegueros-Lepe ◽  
Arturo Veloz-Guerrero
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Energy ◽  
Fundamental Aspect ◽  
Smart Devices ◽  
Battery Life ◽  
Bluetooth Low Energy ◽  
Development Platform ◽  
Power Application ◽  
Hardware Platforms

Internet of things (IoT) has become a very important business segment for the industry since it is estimated that 50 billion devices will be interconnected by 2020, where 30% of them are forecasted to use Bluetooth low energy as the enabling communication protocol. IoT involves smart devices that can be connected to the cloud in order to share and process all types of data collected through sensors. Moreover, 100% of smartphones and tablets shipped in 2018 include Bluetooth low energy, which will allow the interoperation with the upcoming 5G standard. As a result, different low-power hardware platforms have become available to either build prototypes, or implement full IoT solutions. One fundamental aspect while choosing a development platform is to analyze the power consumption of its components to build an optimal low-power application and extend the battery life. In this work, we present current consumption measurements of four Bluetooth low energy commercial platforms configured as central and as peripheral devices, these measurements are aimed to provide the data that are not available in the datasheets and which is needed to select, in an optimal way, the proper connection parameters for the protocol.

scholarly journals Optimum Layout of Low Power LC-Based Digitally Controlled Oscillator for Bluetooth Low Energy in a 4G/5G LTE System

2021 ◽  
Vol 11 (3) ◽  
pp. 1059
Author(s):  
Min-Su Kim ◽  
Sang-Sun Yoo
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Phase Noise ◽  
Supply Voltage ◽  
Low Energy ◽  
Superior Performance ◽  
Bluetooth Low Energy ◽  
Digitally Controlled ◽  
Digitally Controlled Oscillator ◽  
Low Phase Noise

This paper presents an optimum layout method of a low-power, digitally controlled oscillator (DCO) for a Bluetooth low-energy (BLE) transceiver in a 4G/5G LTE system. For the optimal LC-based DCO layout, three different layouts, including different gm cell locations and an Al metal layer, were implemented, and performance was compared and verified for BLE application. The implemented neck DCO (NDCO), where the gm cell is located in the neck of the main inductor, showed superior performance compared to other layouts in terms of low phase noise and low power consumption. The designed NDCO had a low phase noise of −116.1 dBc/Hz at 1 MHz with a 0.5 mW power consumption. The supply voltage and oscillation frequency range were 0.8 V and 4.7–5.7 GHz, respectively, and the NDCO designed with the optimal layout had a good figure-of-merit of −192.6 dBc/Hz.

Low power aware pulse triggered flip flops using modified clock gating approaches

2018 ◽  
Vol 15 (6) ◽  
pp. 792-803
Author(s):  
Sudhakar Jyothula
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Average Power ◽  
Essential Element ◽  
Battery Life ◽  
Portable Devices ◽  
Clock Gating ◽  
Flip Flop ◽  
Content Type ◽  
Low Leakage

PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

scholarly journals A Glitch-Free Novel DET-FF in 22 nm CMOS for Low-Power Application

2018 ◽  
Vol 2018 ◽  
pp. 1-6 ◽  
Author(s):  
Sumitra Singar ◽  
N. K. Joshi ◽  
P. K. Ghosh
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Vlsi Design ◽  
Total System ◽  
Clock Frequency ◽  
Flip Flop ◽  
Digital Vlsi ◽  
Feedback Structure ◽  
Power Application

Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET) techniques. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In the proposed design, we have used an internal dual feedback structure. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system.

Bluetooth Low-Energy-Based Applications

2018 ◽  
pp. 95-112
Author(s):  
Smita Sanjay Ambarkar ◽  
Rakhi Dattatraya Akhare
Keyword(s):  
Indoor Localization ◽  
Low Energy ◽  
Smart Devices ◽  
The Internet ◽  
Bluetooth Low Energy ◽  
Iot Applications ◽  
Proximity Detection ◽  
Battery Power ◽  
Commercial Market ◽  
The Internet Of Things

This chapter focuses on the comprehensive contents of various applications and principles related to Bluetooth low energy (BLE). The internet of things (IoT) applications like indoor localization, proximity detection problem by using Bluetooth low energy, and enhancing the sales in the commercial market by using BLE have the same database requirement and common implementation idea. The real-world applications are complex and require intensive computation. These computations should take less time, cost, and battery power. The chapter mainly focuses on the usage of BLE beacons for indoor localization. The motive behind the study of BLE devices is that it is supported by mobile smart devices that augment its application exponentially.

DESIGNING LOW POWER OF SIGMA DELTA MODULATOR FOR BIOMEDICAL APPLICATION

2005 ◽  
Vol 17 (04) ◽  
pp. 181-185 ◽  
Author(s):  
HO-YIN LEE ◽  
CHEN-MING HSU ◽  
SHENG-CHIA HUANG ◽  
YI-WEI SHIH ◽  
CHING-HSING LUO
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Biomedical Application ◽  
Loop Filter ◽  
Biomedical Signal ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Power Application

This paper discusses the design of micro power Sigma-delta modulator with oversampling technology. This Sigma-delta modulator design is paid special attention to its low power application of portable electronic system in digitizing biomedical signals such as Electro-cardiogram (ECG), Electroencephalogram (EEG) etc. [1]. A high performance, low power second order Sigma-delta modulator is more useful in analog signal acquisition system. Using Sigma-delta modulator can reduce the power consumption and cost in the whole system. The original biomedical signal can be reconstructed by simply applying the digital bit stream from the modulator output through a low-pass filter. The loop filter of this modulator has been implemented by using switch capacitor (SC) integrators and using simple circuitry consists of OpAmps, Comparator and DAC. In general, the resolution of modulator is about 10 bits for biomedical application. In this two order Sigma-delta modulator simulation results of the 1.8V sigma delta modulator show a 68 dB signal-to-noise-and-distortion ratio (SNDR) in 4 kHz biomedical signal bandwidth and a sampling frequency equal to 1 MHz in the 0.18 μ m CMOS technology. The power consumption is 400 μ W. It is very suitable for low power application of biomedical instrument design.

scholarly journals A Fully Integrated Bluetooth Low-Energy Transceiver with Integrated Single Pole Double Throw and Power Management Unit for IoT Sensors

Sensors ◽  
2019 ◽  
Vol 19 (10) ◽  
pp. 2420 ◽  
Author(s):  
Sung Jin Kim ◽  
Dong Gyu Kim ◽  
Seong Jin Oh ◽  
Dong Soo Lee ◽  
Young Gun Pu ◽  
...  
Keyword(s):  
Low Power ◽  
Power Management ◽  
Low Noise ◽  
Buck Converter ◽  
Low Energy ◽  
Management Unit ◽  
Load Current ◽  
Bluetooth Low Energy ◽  
Current Consumption ◽  
Power Management Unit

This paper presents a low power Gaussian Frequency-Shift Keying (GFSK) transceiver (TRX) with high efficiency power management unit and integrated Single-Pole Double-Throw switch for Bluetooth low energy application. Receiver (RX) is implemented with the RF front-end with an inductor-less low-noise transconductance amplifier and 25% duty-cycle current-driven passive mixers, and low-IF baseband analog with a complex Band Pass Filter(BPF). A transmitter (TX) employs an analog phase-locked loop (PLL) with one-point GFSK modulation and class-D digital Power Amplifier (PA) to reduce current consumption. In the analog PLL, low power Voltage Controlled Oscillator (VCO) is designed and the automatic bandwidth calibration is proposed to optimize bandwidth, settling time, and phase noise by adjusting the charge pump current, VCO gain, and resistor and capacitor values of the loop filter. The Analog Digital Converter (ADC) adopts straightforward architecture to reduce current consumption. The DC-DC buck converter operates by automatically selecting an optimum mode among triple modes, Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), and retention, depending on load current. The TRX is implemented using 1P6M 55-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology and the die area is 1.79 mm2. TRX consumes 5 mW on RX and 6 mW on the TX when PA is 0-dBm. Measured sensitivity of RX is −95 dBm at 2.44 GHz. Efficiency of the DC-DC buck converter is over 89% when the load current is higher than 2.5 mA in the PWM mode. Quiescent current consumption is 400 nA from a supply voltage of 3 V in the retention mode.

Research of Low Power Design Strategy Based on IEEE 1801 Unified Power Format

2014 ◽  
Vol 981 ◽  
pp. 21-24
Author(s):  
Shu Ping Cui ◽  
Chuang Xie
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
High Power ◽  
Low Power Design ◽  
Design Strategy ◽  
Design Flow ◽  
Battery Life ◽  
Electronic Systems ◽  
High Power Consumption

Power consumption is becoming an increasingly important aspect of circuit design. High power consumption can lead to high machine temperature, short battery life which makes laptop electronics difficult to be widely used. IEEE 1801 Unified Power Format (UPF) is designed to express power intent for electronic systems and components .This paper first introduces the power principles, puts forward the approaches to reduce power consumption according to UPF, and then demonstrates the Synopsys design flow based on UPF, finally gives the power report and makes a conclusion.

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