More Discussions on Intrinsic Frequency Detection Capability of Full-Rate Linear Phase Detector in Clock and Data Recovery

Electronics ◽

10.3390/electronics7060093 ◽

2018 ◽

Vol 7 (6) ◽

pp. 93 ◽

Cited By ~ 1

Author(s):

Sangjin Byun

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Phase Detector ◽

Linear Phase ◽

Detection Capability ◽

Intrinsic Frequency ◽

Frequency Detection ◽

Full Rate

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A 400 Mb/s∼2.5 Gb/s Referenceless CDR IC Using Intrinsic Frequency Detection Capability of Half-Rate Linear Phase Detector

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2016.2587751 ◽

2016 ◽

Vol 63 (10) ◽

pp. 1592-1604 ◽

Cited By ~ 5

Author(s):

Sangjin Byun

Keyword(s):

Phase Detector ◽

Linear Phase ◽

Detection Capability ◽

Intrinsic Frequency ◽

Frequency Detection

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A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-${\rm \mu}\hbox{m}$ CMOS Technology

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2008.2008520 ◽

2009 ◽

Vol 56 (1) ◽

pp. 6-10 ◽

Cited By ~ 22

Author(s):

Young-Suk Seo ◽

Jang-Woo Lee ◽

Hong-Jung Kim ◽

Changsik Yoo ◽

Jae-Jin Lee ◽

...

Keyword(s):

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery ◽

Phase Detector ◽

Linear Phase

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A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector

IEEE Journal of Solid-State Circuits ◽

10.1109/4.918913 ◽

2001 ◽

Vol 36 (5) ◽

pp. 761-768 ◽

Cited By ~ 187

Author(s):

J. Savoj ◽

B. Razavi

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Phase Detector ◽

Linear Phase

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1–5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector

IET Circuits Devices & Systems ◽

10.1049/iet-cds.2013.0023 ◽

2013 ◽

Vol 7 (3) ◽

pp. 159-168 ◽

Cited By ~ 8

Author(s):

Sangjin Byun ◽

Chung Hwan Son ◽

Jongil Hwang ◽

Byung‐Hun Min ◽

Mun‐Yang Park ◽

...

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Phase Detector ◽

Linear Phase ◽

Phase Offset ◽

Static Phase ◽

Static Phase Offset

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Design of half-rate linear phase detector using MOS current-mode logic gates for 10-Gb/s clock and data recovery circuit

10.1109/icact.2005.245826 ◽

2005 ◽

Cited By ~ 1

Author(s):

Jong-Kil Shin ◽

Tae-Whan Yoo ◽

Man-Seop Lee

Keyword(s):

Logic Gates ◽

Current Mode ◽

Clock And Data Recovery ◽

Data Recovery ◽

Phase Detector ◽

Linear Phase ◽

Current Mode Logic

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A 2.5-Gb/s Clock and Data Recovery Circuit with a 1/4 -Rate Linear Phase Detector

2005 International Conference on Microelectronics ◽

10.1109/icm.2005.1590037 ◽

2006 ◽

Author(s):

S.M. Alavi ◽

O. Shoaei

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Phase Detector ◽

Linear Phase

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A 2.5-Gb/s CMOS Clock And Data Recovery Circuit With A 1/4 Rate Linear Phase Detector And Lock Detector

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. ◽

10.1109/mixdes.2006.1706562 ◽

2006 ◽

Author(s):

S.M. Alavi ◽

O. Shoaei

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Phase Detector ◽

Linear Phase

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A monolithic 622Mb/s half rate clock and data recovery circuit utilizing a novel linear phase detector

2004 IEEE Region 10 Conference TENCON 2004. ◽

10.1109/tencon.2004.1414941 ◽

2005 ◽

Author(s):

Chen Hau Jiun ◽

Tun Zainal ◽

A. Zulkifli ◽

Z. Ali ◽

A. Aziz ◽

...

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Phase Detector ◽

Linear Phase

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A 10Gb/s CMOS Clock and Data Recovery Circuit with a HalfRate Linear Phase Detector

Phase-Locking in High-Performance Systems ◽

10.1109/9780470545492.ch82 ◽

2009 ◽

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Phase Detector ◽

Linear Phase

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A 1/4-RATE LINEAR PHASE DETECTOR FOR HIGH SPEED PLL-BASED CLOCK AND DATA RECOVERY CIRCUIT

Journal of Circuits System and Computers ◽

10.1142/s0218126614500728 ◽

2014 ◽

Vol 23 (05) ◽

pp. 1450072 ◽

Cited By ~ 2

Author(s):

SOMAYEH ADIBIFARD ◽

SEYYED HASSAN MOUSAVI ◽

SOHEYL ZIABAKHSH ◽

MUSTAPHA C. E. YAGOUB

Keyword(s):

Power Consumption ◽

Delay Time ◽

High Speed ◽

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery ◽

Phase Detector ◽

Linear Phase ◽

Lower Power ◽

Reference Signals

A novel 1/4-rate clock phase detector (PD) structure for phase locked loop (PLL)-based clock and data recovery (CDR) is proposed. In this topology, the retimed data is generated within the circuit and no extra circuit is required. Furthermore, the error and reference signals are independent of delay time through gates and thus, no extra replica circuit is needed to compensate such delay. Designed in a 0.18-μm CMOS technology, the proposed 10 Gb/s PD consumes 30 mA from a 1.8 V supply, resulting in a lower power consumption for high-speed applications compared to conventional topologies.

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