scholarly journals Hardware Activation by Means of PUFs and Elliptic Curve Cryptography in Field-Programmable Devices

Electronics ◽  
2016 ◽  
Vol 5 (4) ◽  
pp. 5 ◽  
Author(s):  
Luis Parrilla ◽  
Encarnación Castillo ◽  
Diego Morales ◽  
Antonio García
Author(s):  
Mohan Rao Thokala

Elliptic curve cryptography processor implemented for point multiplication on field programmable gate array. Segmented pipelined full-precision multiplier is used to reduce the latency and also data dependency can be avoided by modifying Lopez-Dahab Montgomery PM Algorithm, results in drastic reduction in the number of clock cycles required. The proposed ECC processor is implemented on Xilinx FPGA families i.e. virtex-4, vitrtex-5, virtex-7.single and three multiplier based designs show the fastest performance compared with reported work individually. Our three multiplier based ECC processor implementation is taking the lowest number of clock cycles on FPGA based design processor.


Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2698
Author(s):  
Muhammad Rashid ◽  
Mohammad Mazyad Hazzazi  ◽  
Sikandar Zulqarnain Khan ◽  
Adel R. Alharbi  ◽  
Asher Sajid  ◽  
...  

This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over GF(2163) with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over GF(2163) is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 μs for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 μW) and Kintex-7 (61 μW) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.


Author(s):  
Kazuki NAGANUMA ◽  
Takashi SUZUKI ◽  
Hiroyuki TSUJI ◽  
Tomoaki KIMURA

Author(s):  
Mohd Javed ◽  
Khaleel Ahmad ◽  
Ahmad Talha Siddiqui

WiMAX is the innovation and upgradation of 802.16 benchmarks given by IEEE. It has numerous remarkable qualities, for example, high information rate, the nature of the service, versatility, security and portability putting it heads and shoulder over the current advancements like broadband link, DSL and remote systems. Though like its competitors the concern for security remains mandatory. Since the remote medium is accessible to call, the assailants can undoubtedly get into the system, making the powerless against the client. Many modern confirmations and encryption methods have been installed into WiMAX; however, regardless it opens with up different dangers. In this paper, we proposed Elliptic curve Cryptography based on Cellular Automata (EC3A) for encryption and decryption the message for improving the WiMAX security


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