scholarly journals Diagnosis of Faults Induced by Radiation and Circuit-Level Design Mitigation Techniques: Experience from VCO and High-Speed Driver CMOS ICs Case Studies

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2144
Author(s):  
Danilo Monda ◽  
Gabriele Ciarpi ◽  
Sergio Saponara

In this paper, we discuss the diagnosis of particle-induced failures in harsh environments such as space and high-energy physics. To address these effects, simulation-before-test and simulation-after-test can be the key points in choosing which radiation hardening by design (RHBD) techniques can be implemented to mitigate or prevent failures. Despite the fact that total ionising dose (TID) has slow but destructive effects overtime on silicon devices, single-event effect (SEE) impulsively disrupts the typical operation of a circuit with temporary or permanent effects. The recently released SpaceFibre protocol drives the current requirements for space applications, and the future upgrade of the LHC experiment scheduled by CERN will require a redesign of the electronic front-end to sustain a radiation level up to the 1 Grad TID level. The effects that these two environments have on two different architectures for high-radiation and high-frequency data transmission are reported, and the efficiency of the mitigation techniques implemented, based on simulations and measurement tests, in the commercial 65 nm technology, are exploited.

1995 ◽  
Vol 416 ◽  
Author(s):  
L. S. Pan

ABSTRACTThis paper will cover two diverse electronic applications for which diamond devices have shown great promise. The first application is diamond radiation sensors for high radiation environments, where the competition is mainly silicon devices. These environments arise in high energy physics experiments, and tests show diamond to be superior to silicon in many ways. The second application is vacuum microelectronics, which generally refers to field emission, where the main competitor is metal and semiconductor microtip arrays. Certain diamond and diamondlike carbon materials emit electrons readily, but the physical mechanisms for this are not well understood. Negative electron affinity and other possible explanations are discussed in this paper.


Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2546
Author(s):  
Alessandro Gabrielli ◽  
Fabrizio Alfonsi ◽  
Alberto Annovi ◽  
Alessandra Camplani ◽  
Alessandro Cerri

In recent years, the technological node used to implement FPGA devices has led to very high performance in terms of computational capacity and in some applications these can be much more efficient than CPUs or other programmable devices. The clock managers and the enormous versatility of communication technology through digital transceivers place FPGAs in a prime position for many applications. For example, from real-time medical image analysis to high energy physics particle trajectory recognition, where computation time can be crucial, the benefits of using frontier FPGA capabilities are even more relevant. This paper shows an example of FPGA hardware implementation, via a firmware design, of a complex analytical algorithm: The Hough transform. This is a mathematical spatial transformation used here to facilitate on-the-fly recognition of the trajectories of ionising particles as they pass through the so-called tracker apparatus within high-energy physics detectors. This is a general study to demonstrate that this technique is not only implementable via software-based systems, but can also be exploited using consumer hardware devices. In this context the latter are known as hardware accelerators. In this article in particular, the Xilinx UltraScale+ FPGA is investigated as it belongs to one of the frontier family devices on the market. These FPGAs make it possible to reach high-speed clock frequencies at the expense of acceptable energy consumption thanks to the 14 nm technological node used by the vendor. These devices feature a huge number of gates, high-bandwidth memories, transceivers and other high-performance electronics in a single chip, enabling the design of large, complex and scalable architectures. In particular the Xilinx Alveo U250 has been investigated. A target frequency of 250 MHz and a total latency of 30 clock periods have been achieved using only the 17 ÷ 53% of LUTs, the 8 ÷ 12% of DSPs, the 1 ÷ 3% of Block Rams and a Flip Flop occupancy range of 9 ÷ 28%.


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