scholarly journals A 0.18-ns Response Time Digital LDO Regulator with Adaptive PI Controller in 180-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (14) ◽  
pp. 1668
Author(s):  
Shengping Lv ◽  
Peiyuan Wan ◽  
Hongda Zhang ◽  
Jiarong Geng ◽  
Jiabao Wen ◽  
...  
Keyword(s):  
Response Time ◽  
Transient Response ◽  
Output Voltage ◽  
Clock Cycle ◽  
Response Speed ◽  
Drop Out ◽  
Cmos Process ◽  
Error Detector ◽  
Current Steps ◽  
Ldo Regulator

Digital low drop-out regulator (D-LDO) with fast settling time and superior transient response is gaining increasing attention to make up for the deficiency of analog LDO. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. In this paper, a multi-bit conversion technique is proposed to improve the transient response speed. The multi-bit conversion technique is achieved by an error detector with adaptive regulation of proportion and integration parameters in the digital controller before pass devices. Besides, a voltage sensor and a time-to-digital converter are employed to convert the output voltage to digital codes. Implemented in a 180-nm CMOS process, the proposed D-LDO features under 36/33 mV of undershoot/overshoot at VOUT = 0.95 V as the load current steps up with 40 mA/1 ns on a 0.5 nF load capacitor. The simulated response time is 0.18-ns, the figure-of-merit of speed FOM1 is 0.65 ps and FOM2 achieves 0.068 pF.

scholarly journals A Fast Transient Response Digital LDO with a TDC-Based Signal Converter

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 132 ◽  
Author(s):  
Hongda Zhang ◽  
Peiyuan Wan ◽  
Jiarong Geng ◽  
Zhaozhe Liu ◽  
Zhijie Chen
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
Supply Voltage ◽  
Clock Cycle ◽  
Response Speed ◽  
Drop Out ◽  
Cmos Process ◽  
Fast Transient Response ◽  
Signal Converter ◽  
Low Supply Voltage

The digital low drop-out regulator (LDO) has been used widely in digital circuits for its low supply voltage characteristics. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. This paper presents a digital LDO to improve transient response speed with a multi-bit conversion technique. The proposed technology uses a voltage sensor and a time-to-digital converter to convert the output voltage to digital codes. Based on a 65-nm CMOS process, the proposed DLDO reduces the settling time from 147.8 ns to 25.2 ns on average and the response speed is improved by about six times.

scholarly journals A Hybrid-Mode LDO Regulator with Fast Transient Response Performance for IoT applications

2021 ◽  
Vol 16 ◽  
pp. 262-274
Author(s):  
Said El Mouzouade ◽  
Karim El Khadiri ◽  
Zakia Lakhliai ◽  
Driss Chenouni ◽  
Ahmed Tahiri
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
Drop Out ◽  
Voltage Regulator ◽  
Hybrid Mode ◽  
Fast Transient Response ◽  
Iot Applications ◽  
Response Performance ◽  
Fast Transient ◽  
Ldo Regulator

A hybrid-mode low-drop out (LDO) voltage regulator with fast transient response performance for IoT applications is proposed in this paper. The proposed LDO regulator consist of two sections. First section is an analog regulator which includes a folded cascode operational amplifier to achieve good PSRR. Second section is current DAC and detectors whitch includes a cource current DAC, sink current DAC, undershoot detectors, and overshoot detectors. The current DAC and detectors are designed to obtain a low drop out and fast transient response. The proposed hybrid-mode LDO voltage regulator has been designed, simulated and layouted in Cadence using TSMC 90 nm CMOS technology. The input range of the LDO regulator is 1.2–2.0 V, and it can produces an output voltage of 1.2V. The LDO regulator achieves 58uA quiescent current, -69 PSRR @ 1 KHz noise frequency and an output voltage drop of around 60mV for a load current step of 100 mA. The final design occupies approximately 0.09 mm2.

Slew Rate and Transient Response Enhancement in MOLDO with Modifying Error Amplifier Structure

2017 ◽  
Vol 26 (12) ◽  
pp. 1750197 ◽  
Author(s):  
Fatemeh Abdi ◽  
Mahnaz Janipoor Deylamani ◽  
Parviz Amiri
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
Input Voltage ◽  
Bias Current ◽  
Cmos Process ◽  
Slew Rate ◽  
Load Current ◽  
Rate Enhancement ◽  
Error Amplifier ◽  
Response Enhancement

In this paper, we use bias current boosting and slew rate enhancement in multiple-output Low-dropout structure to achieve a faster transient response. This method reduces ripples of output voltage during sudden changes in load current and input voltage. The proposed MOLDO circuit was simulated with a 0.18[Formula: see text][Formula: see text]m CMOS process in buck mode with four-output legs. Integrating of proposed circuit is easier because there is the symmetry in the circuit designing. The results of our work show that when input voltage changes between 2.5–3.3[Formula: see text]V, the output voltage after 25[Formula: see text][Formula: see text]s with load current of 100[Formula: see text]mA, is determined with ripple less than 1.8[Formula: see text]mV. In sudden changes, the load current at the range 0–100[Formula: see text]mA, and output voltages after a maximum 15.5[Formula: see text][Formula: see text]s with an input voltage of 3.3[Formula: see text]V have the highest ripple in output voltage of 4[Formula: see text]mV.

A HIGH EFFICIENCY ADAPTIVE CURRENT MODE STEP-UP/STEP-DOWN DC–DC CONVERTER WITH FOUR MODES FOR SMOOTH TRANSITION

2014 ◽  
Vol 23 (07) ◽  
pp. 1450097 ◽  
Author(s):  
YANZHAO MA ◽  
SHAOXI WANG ◽  
SHENGBING ZHANG ◽  
XIAOYA FAN
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
High Efficiency ◽  
Current Mode ◽  
Smooth Transition ◽  
Maximum Efficiency ◽  
Cmos Process ◽  
Voltage Ripple ◽  
Transition Modes ◽  
Step Down

This paper presents a current mode step-up/step-down DC–DC converter with high efficiency, small output voltage ripple, and fast transient response. The control scheme adaptively configures the converter into the proper operation mode. The efficiency is improved by reducing the switching loss, wherein the converter operates like a buck or boost converter, and conduction loss, wherein the average inductor current is reduced in transition modes. The output voltage ripple is significantly reduced by incorporating two constant time transition modes. A fast line transient response is achieved with small overshoot and undershoot voltage. An adaptive substrate selector (ASS) is introduced to dynamically switch the substrate of PMOS power transistors to the highest on-chip voltage. A lossless self-biased current sensor with high-speed and high-accuracy is also achieved. The proposed converter was designed with a standard 0.5 μm CMOS process, and can regulate an output voltage within the input voltage ranged from 2.5 V to 5.5 V. The maximum load current is 600 mA, and the maximum efficiency is 94%. The output voltage ripple is less than 15 mV in all operation modes.

An Output-Capacitorless Ultra-Low Power Low-Dropout Regulator

2017 ◽  
Vol 26 (12) ◽  
pp. 1750193 ◽  
Author(s):  
Xin Cheng ◽  
Hongyu Liang ◽  
Longjie Du ◽  
Zhang Zhang ◽  
Maoxiang Yi ◽  
...  
Keyword(s):  
Transient Response ◽  
Cmos Process ◽  
Heavy Load ◽  
Ultra Low Power ◽  
Chip Area ◽  
Error Amplifier ◽  
Light Load ◽  
Gain Stage ◽  
Ldo Regulator ◽  
Overshoot And Undershoot

This paper proposes an output-capacitorless low-dropout (LDO) regulator with ultra-low quiescent power. It applies an adaptive error amplifier to improve the bandwidth and transient response during heavy load, and a second gain stage to improve the stability during light load. Furthermore, an overshoot and undershoot reduction circuit is used to shorten the settling time when output load is changed. The LDO is fabricated in 0.18[Formula: see text][Formula: see text]m CMOS process and occupies a chip area of 0.06[Formula: see text]mm2. The LDO is measured to output a stable voltage at 1.6[Formula: see text]V with a quiescent power of 1.8[Formula: see text][Formula: see text]W. The experimental results also show a good transient response.

A 2 × VDD-Enabled Output-Capacitor-Free Low-Dropout Regulator with Fast Transient Response for Low-Cost System-on-Chip

2018 ◽  
Vol 27 (09) ◽  
pp. 1850143
Author(s):  
Shuangxing Zhao ◽  
Chenchang Zhan ◽  
Guigang Cai
Keyword(s):  
Transient Response ◽  
Low Voltage ◽  
System On Chip ◽  
Cmos Process ◽  
Fast Transient Response ◽  
Power Transistors ◽  
Fast Transient ◽  
On Chip ◽  
Output Capacitor ◽  
Ldo Regulator

This paper presents a [Formula: see text]-enabled output-capacitor-free CMOS low-dropout (LDO) regulator with fast transient response for cost-effective system-on-chip (SoC) power management applications with elevated-[Formula: see text] supply. All the MOS transistors used in the proposed LDO regulator are low voltage (LV) MOSFETs, hence saving the high voltage devices fabrication cost required in a conventional design. Two LV power transistors are cascaded in the power train. A mid-rail regulator is used to generate [Formula: see text] voltage for the power transistors as well as the main error amplifier to guarantee safe operation. The mid-rail regulator employs stacking transistors to handle the high supply voltage. Moreover, Miller compensation with adaptive biasing is used to achieve good stability and fast transient response. A proof-of-concept design is fabricated in a standard 0.18-[Formula: see text]m CMOS process which achieves 3.3–3.6[Formula: see text]V nominal input, 3.1[Formula: see text]V nominal output and 100[Formula: see text]mA loading capability with all the transistors being 1.8[Formula: see text]V MOSFETs.

scholarly journals A Dual Frequency Compensation Technique to Improve Stability and Transient Response for a Three Stage Low-Drop-Out Linear Regulator

2021 ◽  
Vol 8 (2) ◽  
pp. 219-229
Author(s):  
Anass Slamti ◽  
Youness Mehdaoui ◽  
Driss Chenouni ◽  
Zakia Lakhliai
Keyword(s):  
Transient Response ◽  
Low Voltage ◽  
Drop Out ◽  
Frequency Compensation ◽  
Dual Frequency ◽  
Load Current ◽  
Voltage Range ◽  
Dominant Pole ◽  
Compensation Technique ◽  
Ldo Regulator

A novel internal compensation technique named dual frequency compensation is proposed to improve the stability and the transient response of the on-chip output capacitor three stage low-drop-out linear voltage regulator (LDO). It exploits a combination of amplification and differentiation to sufficiently separate the dominant pole from the first non-dominant pole so that the latter is located after the unity gain frequency regardless of the load current value. The proposed LDO regulator is analyzed, designed, and simulated in standard 0.18 µm low voltage CMOS technology. The presented LDO regulator delivers a stable voltage of 1.2 V for an input supply voltage range of 1.35-1.85 V with a maximum line deviation of 4.68mV/V and can supply up to 150mA of the load current. The maximum transient variation of the output voltage is 54.5 mV when the load current pulses from 150mA to 0mA during a fall time of 1µs. The proposed LDO regulator has a low figure of merit compared with recent LDO regulators.

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