scholarly journals Area Optimization Techniques for High-Density Spin-Orbit Torque MRAMs

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 792
Author(s):  
Yeongkyo Seo ◽  
Kon-Woo Kwon
Keyword(s):  
High Reliability ◽  
Random Access ◽  
Spin Transfer Torque ◽  
Optimization Techniques ◽  
High Density ◽  
Spin Orbit ◽  
Horizontal Dimension ◽  
Area Reduction ◽  
Source Line ◽  
Area Optimization

This paper presents area optimization techniques for high-density spin-orbit torque magnetic random-access memories (SOT-MRAMs). Although SOT-MRAM has many desirable features of nonvolatility, high reliability and low write energy, it poses challenges to high-density memory implementation because of the use of two access transistors per cell. We first analyze the layout of the conventional SOT-MRAM bit-cell that includes two vertical metal lines, a bit-line and a source-line, limiting the horizontal dimension. We further propose two design techniques to reduce the horizontal dimension by decreasing the number of metal lines per cell without any performance overhead. Based on the fact that adjacent columns in a bit-interleaved array are not simultaneously accessed, the proposed techniques share a single source-line between two consecutive bit-cells in the same row. The simulation result shows that proposed techniques can achieve a bit-cell area reduction of 10–25% compared to the conventional SOT-MRAM. The comparison of our proposed designs with the standard spin-transfer torque MRAM shows 45% lower write energy, 84% lower read energy, and 2.3 × higher read-disturb margin.

Spin–Orbit Torques in Metallic Magnetic Multilayers: Challenges and New Opportunities

SPIN ◽  
2017 ◽  
Vol 07 (03) ◽  
pp. 1740013 ◽  
Author(s):  
Tao Wang ◽  
John Q. Xiao ◽  
Xin Fan
Keyword(s):  
Giant Magnetoresistance ◽  
Rapid Development ◽  
Measurement Techniques ◽  
Random Access ◽  
Magnetic Multilayers ◽  
Spin Transfer Torque ◽  
Spin Torque ◽  
Great Effort ◽  
Spin Orbit ◽  
Practical Applications

Two decades after the discovery of the giant magnetoresistance that revolutionizes the hard disk drive, the rapid development of spin torque-based magnetic random access memory has once again demonstrated the great potential of spintronics in practical applications. While the industrial application is mainly focusing on the implementation of current-induced spin transfer torque (STT) in magnetic tunnel junctions, a new type of spin torque emerges due to the spin–orbit interaction in magnetic multilayers. A great effort has been devoted by the scientific community to study the so-called spin–orbit torque (SOT), which is not only of interest to fundamental science, but also exhibits potential for the application of current-induced magnetization switching. In this paper, we will review recent development in the SOTs including the fundamental understanding, materials development and measurement techniques. We will also discuss the challenges of using the SOT in potential applications, particularly on the switching of perpendicularly magnetized films.

scholarly journals Challenges and Applications of Emerging Nonvolatile Memory Devices

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1029 ◽  
Author(s):  
Writam Banerjee
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Random Access ◽  
Random Access Memory ◽  
Spin Transfer Torque ◽  
High Density ◽  
Memory Storage ◽  
Access Memory ◽  
Ultra Low Power

Emerging nonvolatile memory (eNVM) devices are pushing the limits of emerging applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Among several alternatives, phase change memory, spin-transfer torque random access memory, and resistive random-access memory (RRAM) are major emerging technologies. This review explains all varieties of prototype and eNVM devices, their challenges, and their applications. A performance comparison shows that it is difficult to achieve a “universal memory” which can fulfill all requirements. Compared to other emerging alternative devices, RRAM technology is showing promise with its highly scalable, cost-effective, simple two-terminal structure, low-voltage and ultra-low-power operation capabilities, high-speed switching with high-endurance, long retention, and the possibility of three-dimensional integration for high-density applications. More precisely, this review explains the journey and device engineering of RRAM with various architectures. The challenges in different prototype and eNVM devices is disused with the conventional and novel application areas. Compare to other technologies, RRAM is the most promising approach which can be applicable as high-density memory, storage class memory, neuromorphic computing, and also in hardware security. In the post-CMOS era, a more efficient, intelligent, and secure computing system is possible to design with the help of eNVM devices.

PRIORITY-DRIVEN AREA OPTIMIZATION IN HIGH-LEVEL SYNTHESIS

2011 ◽  
Vol 20 (06) ◽  
pp. 1131-1163
Author(s):  
MARIA ABI SAAD ◽  
IYAD OUAISS
Keyword(s):  
Simulated Annealing ◽  
Execution Time ◽  
Annealing Process ◽  
Optimization Techniques ◽  
High Level Synthesis ◽  
Area Reduction ◽  
Area Optimization ◽  
Functional Units ◽  
Priority Function ◽  
High Level

One of the major enhancements that can be made to the high-level synthesis (HLS) process is reducing the overall area of a design in order to either decrease the manufacturing costs or to introduce more functionality to the circuit. Optimizing the area of the datapath is considered a primary field of research in HLS. This work proposes an approach to reduce the area in field programmable gate array (FPGA) by simultaneously tackling the three central tasks of HLS. Scheduling, allocation, and binding are performed and the optimal solution based on area reduction is obtained by using simulated annealing with a priority function. The aim of the priority function is to guide the simulated annealing process into finding the best solution while at the same time incurring the least possible execution time. In order to achieve better results than the initial solution, rescheduling, swapping operations between functional units, swapping variables between registers, and swapping inputs to functional units are considered in the annealing process. A cost function is devised to evaluate a potential move's success or failure. The simulation environment "Eridanus" has been developed in order to support implementation and testing. Several benchmarks were tested and the numerical results consisting of the execution time along with the best solution were recorded to illustrate the performance of the proposed technique. Area reduction was obtained compared to the conventional HLS flow; furthermore, an average substantial reduction in design space exploration time was obtained compared to non-priority based area optimization techniques.

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