scholarly journals Digital Compensation of a Resistive Voltage Divider for Power Measurement

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 696
Author(s):  
Martin Dadić ◽  
Petar Mostarac ◽  
Roman Malarić ◽  
Jure Konjevod
Keyword(s):  
Phase Angle ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Voltage Divider ◽  
Electrical Circuit ◽  
Fine Tuning ◽  
Power Measurement ◽  
Maximum Magnitude ◽  
Digital Filtration ◽  
Digital Compensation

The paper presents a method for digital compensation of the ratio and phase angle errors of a resistive voltage divider. The system consists of a separate electrical circuit of a resistive divider, and a digital compensation system based on National Instruments (NI) PCI eXtension for Instrumentation (PXI) PXI-5922 digital acquisition cards (DAQ). A novel approach to the real-time compensation is presented, using digital signal processing. The algorithm is based on Wiener filtering and finite-impulse-response (FIR) filters. The proposed digital compensation, using FIR digital filtration and NI PXI DAQs, gives maximum magnitude error below 400 ppm and the phase angle error below 4500 μrad, in the frequency band 50 Hz–100 kHz. The algorithm allows the fine-tuning of the compensation to adjust to the possible change in the original transfer function due to the aging of the components.

scholarly journals FPGA Implementation of Proficient 16-Tap FIR Filter Design Using Decision Tree Algorithm

2021 ◽  
Vol 12 (5) ◽  
pp. 170-180
Author(s):  
A Murali, K Hari Kishore
Keyword(s):  
Signal Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Channel Structure ◽  
Decision Tree Algorithm ◽  
Variable Size ◽  
Structure Channel ◽  
Fir Filter Design ◽  
Dsp Applications

Lately, channel is one of the key components in signal handling applications. Among different channels, Finite Impulse Response (FIR) channel is broadly utilized in Digital Signal Processing (DSP) applications for shifting/denoising. For enormous scope coordination (VLSI) execution of fixed-coefficient FIR channels, huge asset used customary multipliers that can be acknowledged by a solitary steady multiplication (SCM) and numerous consistent augmentations (MCM) square utilizing movement and include/take away tasks. For a proficient execution, a variable size apportioning approach is proposed in direct structure channel structure that devours less zone and 11% of decrease in basic way delay, 40% decrease of all out force utilization, 15% decrease of zone delay product(ADP), 52% decrease of vitality delay product(EDP), and 42% decrease of intensity territory product(PAP), on a normal, over the cutting edge techniques. In this paper, a state choice tree calculation is proposed to decrease unpredictability in channel tap cells of variable size apportioning approach. The proposed plot creates a choice tree to perform move and expansion/deduction and aggregation dependent on the consolidated SCM/MCM approach. This plan diminishes the quantity of postpone registers required for tab cells. The proposed snake design will be actualized in Xilinx Zed, Spartan and Virtex devices and Area, power and speed investigation will be performed.

Approximation and the point of flicker-noise formation

2021 ◽  
Author(s):  
A.S. Matsaev
Keyword(s):  
Spectral Density ◽  
Flicker Noise ◽  
Electronic Devices ◽  
Electrical Circuit ◽  
Maximum Magnitude ◽  
Noise Characteristics ◽  
Exponential Increase ◽  
Accurate Definition ◽  
Definition Of ◽  
Flat Section

The article refers to the field of research of noise fluctuations or flicker noise in electronic amplifiers and is devoted to the exact definition of the magnitude and shape of the spectral density of flicker-noise. The 1/f approximation of flicker noise is analyzed and the problem of its non-constructiveness in analyzing the noise characteristics of electronic amplifiers is shown. To eliminate this problem, the mechanism of physical formation of the envelope, a form of spectral density flicker-noise is defined. The physics of flicker-noise is detailed by accurate definition of the place of its formation. An accurate definition of the maximum difference of the amplifier flickernoise on the flat section of noise characteristics is given, using an explanation of the physics of flicker noise. The mechanism and conditions of the exponential increase of flicker noise and its subsequent exponential desire for maximum magnitude are explained. A simple physical approximation is given to determine the processes of forming the envelope form of the spectral density of flickernoise. The physical understanding of the formation of spectral density of flicker-noise tension in the internal structure of the transistor with the participation of external circuits of the amplifier electrical circuit is detailed. The results of the study will help developers to solve many problems of building electronic devices and optimizing their characteristics at a qualitatively new level.

Study of an accurate electronic power measurement technique using modified current transformer and potential transformer

2019 ◽  
Vol 41 (13) ◽  
pp. 3666-3678
Author(s):  
Sirshendu Saha ◽  
Saikat Kumar Bera ◽  
Hiranmoy Mandal ◽  
Pradip Kumar Sadhu ◽  
Satish Chandra Bera
Keyword(s):  
Phase Angle ◽  
Measurement Errors ◽  
Light Emitting Diode ◽  
Current Transformer ◽  
Power Measurement ◽  
Measurement Unit ◽  
Measurement Circuit ◽  
Angle Error ◽  
Ratio Error ◽  
High Tension

In high tension power measurement, potential transformer (PT) and current transformer (CT) are used in order to reduce high tension voltage and current, respectively. But both PT and CT suffer from ratio error and phase angle error, which may produce severe error in power measurement. In the present paper, modified designs of PT and CT are combined to develop an electronic power measurement circuit in order to reduce the measurement errors. The modified PT and CT have reduced phase angle error and ratio error. In the power measurement circuit, the instantaneous product of the outputs of these PT and CT is determined by using a simple light emitting diode (LED)-light dependent register (LDR) or LED-LDR-based product circuit. The operation of the proto type power measurement unit designed in the present work has been experimentally tested and the measured outputs are compared with the readings of laboratory standard wattmeter. The experimental results are reported in the paper. Very good linear characteristics are observed.

scholarly journals Efficient Implementation of Multichannel FM and T-DMB Repeater in FPGA with Automatic Gain Controller

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 482
Author(s):  
Mangi Han ◽  
Youngmin Kim
Keyword(s):  
High Performance ◽  
Electronic Device ◽  
Finite Impulse Response ◽  
Parallel Implementation ◽  
Power Level ◽  
Digital Signal ◽  
Digital Circuit ◽  
Output Power Level ◽  
Verilog Hdl ◽  
Field Programmable

In this study, we implemented a high-performance multichannel repeater, both for FM and T-Digital Multimedia Broadcasting (DMB) signals using a Field Programmable Gate Array (FPGA). In a system for providing services using wireless communication, a radio-shaded area is inevitably generated due to various obstacles. Thus, an electronic device that receives weak or low-level signals and retransmits them at a higher level is crucial. In addition, parallel implementation of digital filters and gain controllers is necessary for a multichannel repeater. When power level is too low or too high, the repeater is required to compensate the power level and ensure a stable signal. However, analog- and software-based repeaters are expensive and they are difficult to install. They also cannot effectively process multichannel in parallel. The proposed system exploits various digital signal-processing algorithms, which include modulation, demodulation, Cascaded Integrator Comb (CIC) filters, Finite Impulse Response (FIR) filters, Interpolated Second Ordered Polynomials (ISOP) filters, and Automatic Gain Controllers (AGCs). The newly proposed AGC is more efficient than others in terms of computation amount and throughput. The designed digital circuit was implemented by using Verilog HDL, and tested using a Xilinx Kintex 7 device. As a result, the proposed repeater can simultaneously handle 40 FM channels and 6 DMB channels in parallel. Output power level is also always maintained by the AGC.

Approximate Compressor-Based Multiplier Design Methodology for Error-Resilient Digital Signal Processing

2020 ◽  
Vol 29 (14) ◽  
pp. 2050233
Author(s):  
Zhixi Yang ◽  
Xianbin Li ◽  
Jun Yang
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Digital Signal Processing ◽  
Resource Utilization ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Electrical Performance ◽  
Approximate Computing ◽  
Dsp Applications

As many digital signal processing (DSP) applications such as digital filtering are inherently error-tolerant, approximate computing has attracted significant attention. A multiplier is the fundamental component for DSP applications and takes up the most part of the resource utilization, namely power and area. A multiplier consists of partial product arrays (PPAs) and compressors are often used to reduce partial products (PPs) to generate the final product. Approximate computing has been studied as an innovative paradigm for reducing resource utilization for the DSP systems. In this paper, a 4:2 approximate compressor-based multiplier is studied. Approximate 4:2 compressors are designed with a practical design criterion, and an approximate multiplier that uses both truncation and the proposed compressors for PP reduction is subsequently designed. Different levels of truncation and approximate compression combination are studied for accuracy and electrical performance. A practical selection algorithm is then leveraged to identify the optimal combinations for multiplier designs with better performance in terms of both accuracy and electrical performance measurements. Two real case studies are performed, i.e., image processing and a finite impulse response (FIR) filter. The design proposed in this paper has achieved up to 16.96% and 20.81% savings on power and area with an average signal-to-noise ratio (SNR) larger than 25[Formula: see text]dB for image processing; similarly, with a decrease of 0.3[Formula: see text]dB in the output SNR, 12.22% and 30.05% savings on power and area have been achieved for an FIR filter compared to conventional multiplier designs.

Design, Development and Analysis of a Voltage Sensor Based on Capacitive Voltage Divider for Smart Grid Applications

2020 ◽  
Author(s):  
João Soares Farias Neto ◽  
Lucas Vinicius Hartmann ◽  
Camila Seibel Gehrke ◽  
Fabiano Salvadori
Keyword(s):  
Fundamental Frequency ◽  
Low Voltage ◽  
Data Communication ◽  
Voltage Divider ◽  
Power Measurement ◽  
Design Development ◽  
Capacitive Voltage ◽  
Phase Deviation ◽  
Capacitive Voltage Divider ◽  
Bidirectional Power Flow

With the recent push for renewable energy several former consumers units now have energy generation capabilities. While this approach is beneficial in general, it also poses new challenges for cooperation and grid stability. The new smartgrid now needs bidirectional power flow, data communication, and intelligent controls in order to ensure reliable operation. Voltage sensing plays a key role, capacitive voltage transformers have been demonstrated useful for high- voltage (100kV+), but have not yet been discussed for low (220V) and medium (13kV) voltage. This paper proposes a simplified capacitive voltage divider circuit for low-voltage measurement. Mathematical modelling is used for steady-state operation, circuit design, and sensitivity to analysis. Monte-Carlo simulations are employed to verify the effect of component tolerances, indicating under 0.7dB gain, and 0.03° error at fundamental frequency. Experimental validation is performed at low-voltage levels (127V), indicating 0.5 dB magnitude and 0.3° phase deviation at fundamental frequency. Performance is also validated from 60Hz to the 50th harmonic, showing 20° phase deviation at the higher order harmonics (16th and up). From the obtained results it is expected that the sensor is sufficient for voltage quality measurements, but should be software-corrected if power measurement is required at the high-order harmonics.

scholarly journals A Signal-Flow-Graph Approach to On-line Gradient Calculation

2000 ◽  
Vol 12 (8) ◽  
pp. 1901-1927 ◽  
Author(s):  
Paolo Campolucci ◽  
Aurelio Uncini ◽  
Francesco Piazza
Keyword(s):  
Neural Network ◽  
Adaptive Systems ◽  
Processing System ◽  
Digital Signal ◽  
Electrical Circuit ◽  
Qualitative Description ◽  
Signal Processing System ◽  
Graph Representations ◽  
Signal Flow ◽  
On Line

A large class of nonlinear dynamic adaptive systems such as dynamic recurrent neural networks can be effectively represented by signal flow graphs (SFGs). By this method, complex systems are described as a general connection of many simple components, each of them implementing a simple one-input, one-output transformation, as in an electrical circuit. Even if graph representations are popular in the neural network community, they are often used for qualitative description rather than for rigorous representation and computational purposes. In this article, a method for both on-line and batch-backward gradient computation of a system output or cost function with respect to system parameters is derived by the SFG representation theory and its known properties. The system can be any causal, in general nonlinear and time-variant, dynamic system represented by an SFG, in particular any feedforward, time-delay, or recurrent neural network. In this work, we use discrete-time notation, but the same theory holds for the continuous-time case. The gradient is obtained in a straightforward way by the analysis of two SFGs, the original one and its adjoint (obtained from the first by simple transformations), without the complex chain rule expansions of derivatives usually employed. This method can be used for sensitivity analysis and for learning both off-line and on-line. On-line learning is particularly important since it is required by many real applications, such as digital signal processing, system identification and control, channel equalization, and predistortion.

NOVEL DESIGN AND FPGA IMPLEMENTATION OF DA-RNS FIR FILTERS

2004 ◽  
Vol 13 (06) ◽  
pp. 1233-1249 ◽  
Author(s):  
WEI WANG ◽  
M. N. S. SWAMY ◽  
M. O. AHMAD
Keyword(s):  
Power Efficiency ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Chinese Remainder Theorem ◽  
Low Cost ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Fpga Implementation ◽  
Fir Filters

Field programmable gate array (FPGA)-based digital signal processing has been widely used in multimedia applications. By combining distributed arithmetic (DA) and residue number system (RNS) in such designs, efficient area, speed and power efficiency can be achieved. In this paper, we propose novel techniques for the design and FPGA implementation of DA-RNS finite impulse response (FIR) filters. By introducing a novel low-cost moduli set and its selection method, efficient modulo arithmetic units inside the subfilters are designed. Then, a new residue-to-binary conversion algorithm, a so-called modified DA Chinese remainder theorem, is derived to reduce the modulo operations and provide an efficient residue-to-binary converter suitable to FPGA implementation. Based on these proposed techniques, a seventh-order DA-RNS FIR filter is designed, implemented and tested by using Xilinx FPGA tools. The implementation results show that the proposed filter design consumes only 77% of the power that the existing filter12,13 requires, while maintaining the same speed (throughput).

Sign in / Sign up

Export Citation Format

Share Document