scholarly journals Arbitrary Configurable 20-Channel Coincidence Counting Unit for Multi-Qubit Quantum Experiment

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 569
Author(s):  
Byung Kwon Park ◽  
Yong-Su Kim ◽  
Young-Wook Cho ◽  
Sung Moon ◽  
Sang-Wook Han

This paper presents a 20-channel coincidence counting unit (CCU) using a low-end field-programmable gate array (FPGA). The architecture of the CCU can be configured arbitrarily to measure from twofold to twentyfold coincidence counts thanks to a multifold controllable architecture, which can be easily manipulated by a graphical user interface (GUI) program. In addition, it provides up to 20 of each input signal count simultaneously. The experimental results show twentyfold coincidence counts with the resolution occurring in a less than 0.5 ns coincidence window. This CCU has appropriate characteristics for various quantum optics experiments using multi-photon qubits.

Author(s):  
Ibtihel Jaziri ◽  
Lotfi Charaabi ◽  
Khaled Jelassi

In this article, the authors present a new approach based on the hardware and software architecture using embedded Linux and field-programmable gate array for implementation of remote laboratories. It combines a set of software and hardware resources in the interest of offering a multidisciplinary low-cost open platform for engineering education. Thus, the proposed approach allows students to develop low-cost and easily programmable prototypes of electrical systems control, robotics, and other embedded devices that feature Internet connectivity, Input/output, networking, and operating systems. In the proposed work, the authors present a codesign solution with flexible hardware devices, providing characteristics of multipurpose use with many experimental devices, and fully configurable graphical user interface. The physical setup and communication principles of hardware architecture are based on two types of devices: the Beaglebone running embedded Linux operating system and the field-programmable logic gate array. The graphical user interface is designed as a web page based on HTML and PHP programming languages; this allows the teachers/students to control the system easily, parameterize, and observe the behavior of the controller/system remotely.


Energies ◽  
2019 ◽  
Vol 12 (6) ◽  
pp. 1016 ◽  
Author(s):  
Guido Ala ◽  
Massimo Caruso ◽  
Rosario Miceli ◽  
Filippo Pellitteri ◽  
Giuseppe Schettino ◽  
...  

The Field Programmable Gate Array (FPGA) represents a valid solution for the design of control systems for inverters adopted in many industry applications, because of both its high flexibility of use and its high-performance with respect to other types of digital controllers. In this context, this paper presents an experimental investigation on the harmonic content of the voltages produced by a three-phase, five level cascaded H-Bridge Multilevel inverter with an FPGA-based control board, aiming also to evaluate the performance of the FPGA through the implementation of the main common modulation techniques and the comparison between simulation and experimental results. The control algorithms are implemented by means of the VHDL programming language. The output voltage waveforms, which have been obtained by applying to the inverter the main PWM techniques, are compared in terms of THD%. Simulation and experimental results are analyzed, compared and finally discussed.


Sensors ◽  
2021 ◽  
Vol 21 (1) ◽  
pp. 308
Author(s):  
Mojtaba Parsakordasiabi ◽  
Ion Vornicu ◽  
Ángel Rodríguez-Vázquez ◽  
Ricardo Carmona-Galán

In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [−0.953, 1.185] LSB, and an integral non-linearity (INL) within [−2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.


2015 ◽  
Vol 54 (15) ◽  
pp. 4727 ◽  
Author(s):  
Byung Kwon Park ◽  
Yong-Su Kim ◽  
Osung Kwon ◽  
Sang-Wook Han ◽  
Sung Moon

2008 ◽  
Author(s):  
Michael Wirthlin ◽  
Brent Nelson ◽  
Brad Hutchings ◽  
Peter Athanas ◽  
Shawn Bohner

2020 ◽  
Vol 91 (10) ◽  
pp. 104707
Author(s):  
Yinyu Liu ◽  
Hao Xiong ◽  
Chunhui Dong ◽  
Chaoyang Zhao ◽  
Quanfeng Zhou ◽  
...  

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