scholarly journals Demonstration of Three True Random Number Generator Circuits Using Memristor Created Entropy and Commercial Off-the-Shelf Components

Entropy ◽  
2021 ◽  
Vol 23 (3) ◽  
pp. 371
Author(s):  
Scott Stoller ◽  
Kristy A. Campbell
Keyword(s):  
Random Number ◽  
Random Number Generator ◽  
Statistical Test ◽  
Test Suite ◽  
Successful Implementation ◽  
Number Generator ◽  
Simple Circuit ◽  
True Random Number Generator ◽  
Commercial Off The Shelf ◽  
Circuit Components

In this work, we build and test three memristor-based true random number generator (TRNG) circuits: two previously presented in the literature and one which is our own design. The functionality of each circuit is assessed using the National Institute of Standards and Technology (NIST) Statistical Test Suite (STS). The TRNG circuits were built using commercially available off-the-shelf parts, including the memristor. The results of this work confirm the usefulness of memristors for successful implementation of TRNG circuits, as well as the ease with which a TRNG can be built using simple circuit designs and off-the-shelf breadboard circuit components.

scholarly journals Testing a hardware random number generator using NIST statistical test suite

Doklady BGUIR ◽  
2021 ◽  
Vol 19 (4) ◽  
pp. 37-42
Author(s):  
M. O. Pikuza ◽  
S. Yu. Mikhnevich
Keyword(s):  
Data Acquisition ◽  
Random Number ◽  
Random Sequence ◽  
Random Number Generator ◽  
Reverse Current ◽  
Statistical Test ◽  
Test Suite ◽  
Number Generator ◽  
Random Number Generators ◽  
Output Sequence

Random number generators are required for the operation of cryptographic information protection systems. For а correct application of the generator in the field of information security, it is necessary that its output sequence to be indistinguishable from a uniformly distributed random sequence. To verify this, it is necessary to test the generator output sequence using various statistical test suites such as Dihard and NIST. The purpose of this work is to test a prototype hardware random number generator. The generator is built on the basis of the ND103L noise diode and has a random digital sequence of binary numbers at the output. In the prototype there is a possibility of regulating the amount of reverse current through the noise diode, as well as setting the data acquisition period, i.e. data generation frequency. In the course of operation, a number of sequences of random numbers were removed from the generator at various values of the reverse current through the noise diode, the period of data acquisition and the ambient temperature. The resulting sequences were tested using the NIST statistical test suite. After analyzing the test results, it was concluded that the generator operates relatively stably in a certain range of initial parameters, while the deterioration in the quality of the generator's operation outside this range is associated with the technical characteristics of the noise diode. It was also concluded that the generator under study is applicable in certain applications and to improve the stability of its operation, it can be improved both in hardware and software. The results of this work can be useful to developers of hardware random number generators built according to a similar scheme.

scholarly journals A Morphable Physically Unclonable Function and True Random Number Generator Using a Commercial Magnetic Memory

2021 ◽  
Vol 11 (1) ◽  
pp. 5
Author(s):  
Mohammad Nasim Imtiaz Khan ◽  
Chak Yuen Cheng ◽  
Sung Hao Lin ◽  
Abdullah Ash-Saki ◽  
Swaroop Ghosh
Keyword(s):  
Standard Deviation ◽  
Correlation Coefficient ◽  
Random Number ◽  
Random Number Generator ◽  
Test Suite ◽  
Magnetic Memory ◽  
Number Generator ◽  
True Random Number Generator

We use commercial magnetic memory to realize morphable security primitives, a Physically Unclonable Function (PUF) and a True Random Number Generator (TRNG). The PUF realized by manipulating the write time and the TRNG is realized by tweaking the number of write pulses. Our analysis indicates that more than 75% bits in the PUF are unusable without any correction due to their inability to exhibit any randomness. We exploit temporal randomness of working columns to fix the unusable columns and write latency to fix the unusable rows during the enrollment. The intra-HD, inter-HD, energy, bandwidth and area of the proposed PUF are found to be 0, 46.25%, 0.14 pJ/bit, 0.34 Gbit/s and 0.385 μm2/bit (including peripherals) respectively. The proposed TRNG provides all possible outcomes with a standard deviation of 0.0062, correlation coefficient of 0.05 and an entropy of 0.95. The energy, bandwidth and area of the proposed TRNG is found to be 0.41 pJ/bit, 0.12 Gbit/s and 0.769 μm2/bit (including peripherals). The performance of the proposed TRNG has also been tested with NIST test suite. The proposed designs are compared with other magnetic PUFs and TRNGs from other literature.

0.4 mW, 0.27 pJ/bit true random number generator using jitter, metastability and current starved topology

2020 ◽  
Vol 14 (7) ◽  
pp. 1001-1011
Author(s):  
Dhirendra Kumar ◽  
Rahul Anand ◽  
Sajai Vir Singh ◽  
Prasanna Kumar Misra ◽  
Ashok Srivastava ◽  
...  
Keyword(s):  
Random Number ◽  
Random Number Generator ◽  
Number Generator ◽  
True Random Number Generator

scholarly journals A High‐Speed True Random Number Generator Based on a Cu x Te 1− x Diffusive Memristor

2021 ◽  
pp. 2100062
Author(s):  
Kyung Seok Woo ◽  
Jaehyun Kim ◽  
Janguk Han ◽  
Jin Myung Choi ◽  
Woohyun Kim ◽  
...  
Keyword(s):  
High Speed ◽  
Random Number ◽  
Random Number Generator ◽  
Number Generator ◽  
True Random Number Generator

scholarly journals True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA

2021 ◽  
Vol 11 (8) ◽  
pp. 3330
Author(s):  
Pietro Nannipieri ◽  
Stefano Di Matteo ◽  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Jacopo Belli ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
Random Number ◽  
Random Number Generator ◽  
Random Number Generation ◽  
Galois Ring ◽  
Number Generator ◽  
True Random Number Generator ◽  
Number Generation ◽  
Field Programmable ◽  
Gate Array

Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.

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