scholarly journals Turbo Decoder Design based on an LUT-Normalized Log-MAP Algorithm

Entropy ◽  
2019 ◽  
Vol 21 (8) ◽  
pp. 814
Author(s):  
Jun Li ◽  
Xiumin Wang ◽  
Jinlong He ◽  
Chen Su ◽  
Liang Shan
Keyword(s):  
Wireless Communication ◽  
Communication Systems ◽  
Lookup Table ◽  
Clock Frequency ◽  
High Complexity ◽  
Decoding Algorithm ◽  
Turbo Decoder ◽  
Map Algorithm ◽  
Map Decoding ◽  
Log Map

Turbo codes have been widely used in wireless communication systems due to their good error correction performance. Under time division long term evolution (TD-LTE) of the 3rd generation partnership project (3GPP) wireless communication standard, a Log maximum a posteriori (Log-MAP) decoding algorithm with high complexity is usually approximated as a lookup-table Log-MAP (LUT-Log-MAP) algorithm and Max-Log-MAP algorithm, but these two algorithms have high complexity and high bit error rate, respectively. In this paper, we propose a normalized Log-MAP (Nor-Log-MAP) decoding algorithm in which the function max* is approximated by using a fixed normalized factor multiplied by the max function. Combining a Nor-Log-MAP algorithm with a LUT-Log-MAP algorithm creates a new kind of LUT-Nor-Log-MAP algorithm. Compared with the LUT-Log-MAP algorithm, the decoding performance of the LUT-Nor-Log-MAP algorithm is close to that of the LUT-Log-MAP algorithm. Based on the decoding method of the Nor-Log-MAP algorithm, we also put forward a normalization functional unit (NFU) for a soft-input soft-output (SISO) decoder computing unit. The simulation results show that the LUT-Nor-Log-MAP algorithm can save about 2.1% of logic resources compared with the LUT-Log-MAP algorithm. Compared with the Max-Log-MAP algorithm, the LUT-Nor-Log-MAP algorithm shows a gain of 0.25~0.5 dB in decoding performance. Using the Cyclone IV platform, the designed Turbo decoder can achieve a throughput of 36 Mbit/s under a maximum clock frequency of 44 MHz.

scholarly journals Efficient MAP-algorithm implementation on programmable architectures

2003 ◽  
Vol 1 ◽  
pp. 259-263 ◽  
Author(s):  
F. Kienle ◽  
H. Michel ◽  
F. Gilbert ◽  
N. Wehn
Keyword(s):  
Turbo Codes ◽  
Communication Systems ◽  
Building Blocks ◽  
Communication Performance ◽  
Channel Decoding ◽  
Turbo Decoder ◽  
Decoding Algorithms ◽  
Map Algorithm ◽  
Algorithm Implementation ◽  
Log Map

Abstract. Maximum-A-Posteriori (MAP) decoding algorithms are important HW/SW building blocks in advanced communication systems due to their ability to provide soft-output informations which can be efficiently exploited in iterative channel decoding schemes like Turbo-Codes. Multi-standards demand flexible implementations on programmable platforms. In this paper we analyze a quantized turbo-decoder based on a Max-Log-MAP algorithm with Extrinsic Scaling Factor (ESF). Its communication performance approximate to a Turbo-Decoder with a Log-MAP algorithm and is less sensitive to quantization effects. We present Turbo-Decoder implementations on state-of-the-art DSPs and show that only a Max-Log-MAP implementation fulfills a throughput requirement of ~2 Mbit/s. The negligible overhead for the ESF implementation strengthen the use of Max-Log-MAP with ESF implementation on programmable platforms.

Improved log-MAP decoding algorithm for turbo-like codes

2006 ◽  
Vol 10 (3) ◽  
pp. 186-188 ◽  
Author(s):  
Hao Wang ◽  
Hongwen Yang ◽  
Dacheng Yang
Keyword(s):  
Decoding Algorithm ◽  
Map Decoding ◽  
Log Map

scholarly journals Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures

2014 ◽  
Vol 63 (3) ◽  
pp. 531-537 ◽  
Author(s):  
Maurizio Martina ◽  
Stylianos Papaharalabos ◽  
P. Takis Mathiopoulos ◽  
Guido Masera
Keyword(s):  
Low Complexity ◽  
Turbo Decoder ◽  
Map Algorithm ◽  
Hardware Architectures ◽  
Log Map

scholarly journals Architecture and Implementation of Fading Compensation for Dynamic Spectrum Access Wireless Communication Systems

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-9
Author(s):  
Masahide Hatanaka ◽  
Toru Homemoto ◽  
Takao Onoye
Keyword(s):  
Wireless Communication ◽  
Communication Systems ◽  
Orthogonal Frequency Division Multiplexing ◽  
Dynamic Spectrum Access ◽  
Dynamic Spectrum ◽  
Wireless Communication Systems ◽  
Clock Frequency ◽  
Spectrum Access ◽  
Ofdm Symbol ◽  
Piecewise Linear Interpolation

This paper proposes an efficient architecture and implementation of fading compensation dedicated to dynamic spectrum access (DSA) wireless communication. Since pilot subcarrier arrangements are adaptively determined in wireless communication systems with DSA, the proposed architecture employs piecewise linear interpolation to the channel response estimation for data subcarriers in order to increase the channel estimation accuracy. The fading compensation for an orthogonal frequency-division multiplexing (OFDM) symbol is performed within the time for one OFDM symbol to make increase of latency smaller. The proposed architecture guarantees real-time processing with 76 MHz or higher clock frequency. The FPGA implementation of the proposed architecture occupies 1,577 slices and works up to 121 MHz.

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