scholarly journals A Scalable and Highly Configurable Cache-Aware Hybrid Flash Translation Layer

Computers ◽  
2014 ◽  
Vol 3 (1) ◽  
pp. 36-57 ◽  
Author(s):  
Jalil Boukhobza ◽  
Pierre Olivier ◽  
Stéphane Rubini
Keyword(s):  
Flash Translation Layer ◽  
Configurable Cache

PCI Express-Based NVMe Solid State Disk

2013 ◽  
Vol 464 ◽  
pp. 365-368 ◽  
Author(s):  
Ji Jun Hung ◽  
Kai Bu ◽  
Zhao Lin Sun ◽  
Jie Tao Diao ◽  
Jian Bin Liu
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Detailed Design ◽  
Pci Express ◽  
Storage Media ◽  
Solid State Disk ◽  
Memory Card ◽  
Non Volatile Memory ◽  
Flash Translation Layer

This paper presents a new architecture SSD based on NVMe (Non-Volatile Memory express) protocol. The NVMe SSD promises to solve the conventional SATA and SAS interface bottleneck. Its aimed to present a PCIe NAND Flash memory card that uses NAND Flash memory chip as the storage media. The paper analyzes the PCIe protocol and the characteristics of SSD controller, and then gives the detailed design of the PCIe SSD. It mainly contains the PCIe port and Flash Translation Layer.

HCFTL: A Locality-Aware Page-Level Flash Translation Layer

2019 ◽  
Author(s):  
Hao Chen ◽  
Cheng Li ◽  
Yubiao Pan ◽  
Min Lyu ◽  
Yongkun Li ◽  
...  
Keyword(s):  
Flash Translation Layer

Hierarchical Request-Size-Aware Flash Translation Layer Based on Page-Level Mapping

2019 ◽  
Vol 28 (07) ◽  
pp. 1950117 ◽  
Author(s):  
Dong Bin Yeo ◽  
Joon-Yong Paik ◽  
Tae-Sun Chung
Keyword(s):  
Flash Memory ◽  
High Speed ◽  
Garbage Collection ◽  
Good Alternative ◽  
Performance Degradation ◽  
Digital Data ◽  
Mass Storage ◽  
Special Area ◽  
Flash Translation Layer ◽  
Request Size

Owing to the increasing Internet population, there has been an explosion in the amount of digital data generated and also an increase in data complexity. This trend is called big data paradigm. As the Internet of Things (IoT) takes center stage, the growth of data will continue to increase. Therefore, the demand for mass storage devices that have high access speed is increasing. Industry has been paying attention to flash memories that can process large amounts of data at high speed. It will be a good alternative for storing and processing ever-increasing amounts of data because of low power consumption, high shock resistance, portability and fast access speed. However, the write speed is about 10–20 times slower than the read speed in flash memory. In addition, write operations are not allowed to be performed with in-place updates. Garbage collection mechanism is proposed in order to solve the problem incurred by the not-in-place update property of write operations. However, garbage collection mechanism unavoidably causes overhead of additional internal operations, which leads to performance degradation. In this paper, to prevent performance degradation caused by garbage collection, we propose a request-size-aware flash translation layer (RSaFTL) and a hierarchical request-size-aware flash translation layer (HiRSaFTL). They are designed based on page-level address translation. In RSaFTL and HiRSaFTL, page-sized data with high temporal locality cluster into a special area called active blocks by exploiting the property of realistic traces. As a result of the experiments, RSaFTL and HiRSaFTL reduce the number of pages migrated during garbage collections by up to 17.9% and 21.3%, respectively, compared with pure page-level flash transition layer.

Flash Translation Layer

2017 ◽  
pp. 129-147
Author(s):  
Jalil Boukhobza ◽  
Pierre Olivier
Keyword(s):  
Flash Translation Layer
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