scholarly journals The Performance of Zr-Doped Al-Zn-Sn-O Thin Film Transistor Prepared by Co-Sputtering

2019 ◽  
Vol 9 (23) ◽  
pp. 5150 ◽  
Author(s):  
Xiaochen Zhang ◽  
Xianzhe Liu ◽  
Kuankuan Lu ◽  
Honglong Ning ◽  
Dong Guo ◽  
...  

In this work, a thin film transistor (TFT) with Zr-doped aluminum-zinc-tin oxide (Zr-AZTO) semiconductor as active layer was investigated. The Zr-AZTO thin films were co-sputtered by ZrO2 and AZTO targets (RF-Sputter) in Ar, and annealed at 350 °C in air atmosphere. With the discharge power of AZTO increasing from 100 W to 120 W, the content of Zr element decreases from 0.63 ± 0.01 at.% to 0.34 ± 0.01 at.%, and the oxygen vacancy decreases from (19.0 ± 0.1)% to (17.3 ± 0.8)%. The results of Zr-AZTO thin film show that the main factor is the co-sputter power of ZrO2 target. With the co-sputter power of ZrO2 increasing from 15 W to 45 W, the content of Zr element increases from 0.63 ± 0.01 at.% to 2.79 ± 0.01 at.%, the content of oxygen vacancy decreases from (19.0 ± 0.1)% to (14.1 ± 0.1)%, Eg increases from 2.76 eV to 2.86 eV, and the root mean square (RMS) roughness firstly decreases from 0.402 nm to 0.387 nm and then increases to 0.490 nm. The Micro Wave Photo Conductivity Decay (μ-PCD, LTA-1620SP) was used to measure the quality of Zr-AZTO thin film and the mean peak and D value decreases from 139.3 mV to 80.9 mV and from 1.54 to 0.77 as the co-sputter power of ZrO2 increases from 15 W to 45 W, which means it has highest localized states and defects in high ZrO2 co-sputter power. The devices prepared at 15 W (ZrO2)/100 W (AZTO) co-sputter show a best performance, with a μsat of 8.0 ± 0.6 cm2/(V∙S), an Ion/Ioff of (2.01 ± 0.34) × 106, and a SS of 0.18 ± 0.03 V/dec. The device of Sample B has a 0.5 V negative shift under −20 V NBS and 9.6 V positive shift under 20 V PBS.

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1099
Author(s):  
Ye-Ji Han ◽  
Se Hyeong Lee ◽  
So-Young Bak ◽  
Tae-Hee Han ◽  
Sangwoo Kim ◽  
...  

Conventional sol-gel solutions have received significant attention in thin-film transistor (TFT) manufacturing because of their advantages such as simple processing, large-scale applicability, and low cost. However, conventional sol-gel processed zinc tin oxide (ZTO) TFTs have a thermal limitation in that they require high annealing temperatures of more than 500 °C, which are incompatible with most flexible plastic substrates. In this study, to overcome the thermal limitation of conventional sol-gel processed ZTO TFTs, we demonstrated a ZTO TFT that was fabricated at low annealing temperatures of 350 °C using self-combustion. The optimized device exhibited satisfactory performance, with μsat of 4.72 cm2/V∙s, Vth of −1.28 V, SS of 0.86 V/decade, and ION/OFF of 1.70 × 106 at a low annealing temperature of 350 °C for one hour. To compare a conventional sol-gel processed ZTO TFT with the optimized device, thermogravimetric and differential thermal analyses (TG-DTA) and X-ray photoelectron spectroscopy (XPS) were implemented.


RSC Advances ◽  
2020 ◽  
Vol 10 (70) ◽  
pp. 42682-42687
Author(s):  
Ting-Ruei Lin ◽  
Li-Chung Shih ◽  
Po-Jen Cheng ◽  
Kuan-Ting Chen ◽  
Jen-Sue Chen

Photonic potentiation and electric depression are realized in a ZTO thin film transistor for the application in neuromorphic computation.


2019 ◽  
Vol 14 (1) ◽  
Author(s):  
Dan-Dan Liu ◽  
Wen-Jun Liu ◽  
Jun-Xiang Pei ◽  
Lin-Yan Xie ◽  
Jingyong Huo ◽  
...  

AbstractAmorphous In–Ga–Zn-O (a-IGZO) thin-film transistor (TFT) memories are attracting many interests for future system-on-panel applications; however, they usually exhibit a poor erasing efficiency. In this article, we investigate voltage-polarity-dependent programming behaviors of an a-IGZO TFT memory with an atomic-layer-deposited ZnO charge trapping layer (CTL). The pristine devices demonstrate electrically programmable characteristics not only under positive gate biases but also under negative gate biases. In particular, the latter can generate a much higher programming efficiency than the former. Upon applying a gate bias pulse of +13 V/1 μs, the device shows a threshold voltage shift (ΔVth) of 2 V; and the ΔVth is as large as −6.5 V for a gate bias pulse of −13 V/1 μs. In the case of 12 V/1 ms programming (P) and −12 V/10 μs erasing (E), a memory window as large as 7.2 V can be achieved at 103 of P/E cycles. By comparing the ZnO CTLs annealed in O2 or N2 with the as-deposited one, it is concluded that the oxygen vacancy (VO)-related defects dominate the bipolar programming characteristics of the TFT memory devices. For programming at positive gate voltage, electrons are injected from the IGZO channel into the ZnO layer and preferentially trapped at deep levels of singly ionized oxygen vacancy (VO+) and doubly ionized oxygen vacancy (VO2+). Regarding programming at negative gate voltage, electrons are de-trapped easily from neutral oxygen vacancies because of shallow donors and tunnel back to the channel. This thus leads to highly efficient erasing by the formation of additional ionized oxygen vacancies with positive charges.


2011 ◽  
Vol 50 (7R) ◽  
pp. 070201 ◽  
Author(s):  
Jee Ho Park ◽  
Won Jin Choi ◽  
Jin Young Oh ◽  
Soo Sang Chae ◽  
Woo Soon Jang ◽  
...  

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