scholarly journals Compact Model for L-Shaped Tunnel Field-Effect Transistor Including the 2D Region

2019 ◽  
Vol 9 (18) ◽  
pp. 3716
Author(s):  
Faraz Najam ◽  
Yun Seop Yu
Keyword(s):  
Electric Field ◽  
Poisson Equation ◽  
Surface Potential ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Compact Model ◽  
Subthreshold Region ◽  
Source Current ◽  
Effect Transistor

The L-shaped tunneling field-effect transistor (LTFET) is the only line-tunneling type of TFET to be experimentally demonstrated. To date, there is no literature available on the compact model of LTFET. In this paper, a compact model of LTFET is presented. LTFET has both one-dimensional (1D) and 2D band-to-band tunneling (BTBT) components. The 2D BTBT part dominates in the subthreshold region, whereas the 1D BTBT dominates at higher gate-source biases. The model consists of 1D and 2D BTBT models. The 2D BTBT model is based on the assumption that the electric field originating from the gate and terminating at the source edge is perfectly circular. Tunneling path length is obtained by calculating the distance along an electric field arc that runs from gate to source. The 1D BTBT model is based on a simultaneous solution of the 1D Poisson equation in source and channel regions. Expressions for electric field and potential obtained from integrating the Poisson equation in source and channel regions are solved simultaneously to find the surface potential. Once the surface potential is known, all the other unknown variables, including junction potential and source depletion length, can be calculated. Using the potential profile, tunneling lengths were found for both the source-to-channel BTBT regime, and channel-to-channel BTBT regime. The tunneling lengths were used to calculate the BTBT tunneling rate, and finally, the drain-source current as a function of gate-source, and drain-source bias was calculated. The model results were compared against technology computer-aided design (TCAD) simulation results and were found to be in reasonable agreement for a compact model.

Surrounding Channel Nanowire Tunnel Field-Effect Transistor with Dual Gate to Reduce a Hump Phenomenon

2020 ◽  
Vol 20 (7) ◽  
pp. 4182-4187
Author(s):  
Ye Sung Kwon ◽  
Seong-Hyun Lee ◽  
Yoon Kim ◽  
Garam Kim ◽  
Jang Hyun Kim ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Control Device ◽  
Subthreshold Region ◽  
Dual Gate ◽  
Technical Issues ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design

The tunnel field-effect transistor (TFET) with surrounding channel nanowire (SCNW) structure promises better performance than the conventional planar TFET in terms of subthreshold swing (SS) and on-current (ION). In spite of the advantages of SCNW TFET, there are some technical issues in the aspects of a hump phenomenon in subthreshold region and a high ambipolar current (IAMB) in off-state. In order to overcome these issues, a novel dual-gate SCNW TFET (DG-SCNW TFET) with differential gate work functions (WFs) and a gate-drain underlap is proposed and studied by using technology computer-aided design (TCAD) simulation. In addition, a hetero-junction with SiGe source is applied to improve the device performance. Finally, it is confirmed that the optimized DG-SCNW TFET shows the remarkable performance comparing with the control device.

Surface-potential-based physical compact model for graphene field effect transistor

2016 ◽  
Vol 120 (8) ◽  
pp. 084509 ◽  
Author(s):  
Lingfei Wang ◽  
Songang Peng ◽  
Wei Wang ◽  
Guangwei Xu ◽  
Zhuoyu Ji ◽  
...  
Keyword(s):  
Surface Potential ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Compact Model ◽  
Graphene Field Effect Transistor ◽  
Effect Transistor

scholarly journals An Analytical Modeling for Dual Source Vertical Tunnel Field Effect Transistor

2019 ◽  
Vol 8 (3) ◽  
pp. 603-608 ◽  
Keyword(s):  
Electric Field ◽  
Surface Potential ◽  
Field Effect ◽  
Analytical Modeling ◽  
Field Effect Transistor ◽  
Poisson Equations ◽  
Dual Source ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Power Application

The given paper proposes the 2D analytical modeling of surface potential and electric field for a Dual Source Vertical Tunnel Field Effect Transistor (DSV-TFET). The 2-D Poisson equations are solved by parabolic approximation method, with the help of suitable boundary conditions and analytical expressions for surface potential and electric field distribution in DSV-TFET. The analytical results of proposed model are compared with simulation results drive using SILVACO TCAD tool, whereas in our proposed device DSV-TFET provides the high on current (ION=1.74×10-4 A/µm), low OFF current (IOFF= 6.92 ×10-13 A/µm), ION/IOFF current ratio in order of 108 to 109 with the minimum point of average subthreshold slope of 3.47 mV/decade which can be used for low power application.

scholarly journals A Physic-Based Explicit Compact Model for Reconfigurable Field-Effect Transistor

IEEE Access ◽  
2021 ◽  
pp. 1-1
Author(s):  
Wangze Ni ◽  
Zhen Dong ◽  
Bairun Huang ◽  
Yichi Zhang ◽  
Zhuojun Chen
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Compact Model ◽  
Effect Transistor

Temperature Sensitivity Analysis of Extended Source Double Gate Tunnel Field Effect Transistor

2021 ◽  
Author(s):  
Dharmender Nishad ◽  
Kaushal Nigam ◽  
Satyendra Kumar
Keyword(s):  
Temperature Sensitivity ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Of Temperature ◽  
Double Gate ◽  
Extended Source ◽  
Temperature Variations ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Abstract Temperature-induced performance variation is one of the main concerns of the conventional stack gate oxide double gate tunnel field-effect transistor (SGO-DG-TFET). In this regard, we investigate the temperature sensitivity of extended source double gate tunnel field-effect transistor (ESDG-TFET). For this, we have analyzed the effect of temperature variations on the transfer characteristics, analog/RF, linearity and distortion figure of merits (FOMs) using technology computer aided design (TCAD) simulations. Further, the temperature sensitivity performance is compared with conventional SGO-DG-TFET. The comparative analysis shows that ESDG-TFET is less sensitive to temperature variations compared to the conventional SGO-DG-TFET. Therefore, this indicates that ESDG-TFET is more reliable for low-power, high-frequency applications at a higher temperature compared to conventional SGO-DG-TFET.

A Large-Signal Monolayer Graphene Field-Effect Transistor Compact Model for RF-Circuit Applications

2017 ◽  
Vol 64 (10) ◽  
pp. 4302-4309 ◽  
Author(s):  
Jorge-Daniel Aguirre-Morales ◽  
Sebastien Fregonese ◽  
Chhandak Mukherjee ◽  
Wei Wei ◽  
Henri Happy ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Compact Model ◽  
Monolayer Graphene ◽  
Large Signal ◽  
Graphene Field Effect Transistor ◽  
Effect Transistor ◽  
Rf Circuit

Partial Dissolution of Charge Order Phase Observed in -(BEDT-TTF)2PF6 Single Crystal Field Effect Transistor

2016 ◽  
Vol 16 (4) ◽  
pp. 3267-3272
Author(s):  
Masatoshi Sakai ◽  
Norifumi Moritoshi ◽  
Shigekazu Kuniyoshi ◽  
Hiroshi Yamauchi ◽  
Kazuhiro Kudo ◽  
...  
Keyword(s):  
Electric Field ◽  
Single Crystal ◽  
Temperature Dependence ◽  
Crystal Field ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Electrical Conductance ◽  
Charge Order ◽  
Crystal Field Effect ◽  
Effect Transistor

The effect of an applied gate electric field on the charge-order phase in β-(BEDT-TTF)2PF6 single-crystal field-effect transistor structure was observed at around room temperature by technical improvement with respect to sample preparation and electrical measurements. A relatively slight but systematic increase of the electrical conductance induced by the applied gate electric field and its temperature dependence was observed at around the metal-insulator transition temperature (TMI). The temperature dependence of the modulated electrical conductance demonstrated that TMI was shifted toward the lower side by application of a gate electric field, which corresponds to partial dissolution of the charge-order phase. The thickness of the partially dissolved charge order region was estimated to be several score times larger than the charge accumulation region.

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