scholarly journals Modulation Linearization Technique for FM/CW SAR Image Processing Using Range Migration

2021 ◽  
Vol 11 (16) ◽  
pp. 7410
Author(s):  
Theodore Grosch ◽  
Cyril Okhio

Linear FMCW radar suffers from impairments in range and range rate if there are errors in the modulation rate or phase discontinuities. Often, this is a result of a nonlinearity of the voltage-controlled oscillator that is in the source of the transmit and receive local oscillator. The nonlinearity can be corrected at the source by using a nonlinear control voltage or by processing the received beat frequency. Any signal processing using the later method leads to computation time and energy costs, which can be considerable in some applications. When the range migration algorithm using the Stolt Transform is used for Synthetic Aperture Radar (SAR) image processing, the autofocus linearization technique described here costs nothing in additional hardware or computation time.

2019 ◽  
Vol 13 (2) ◽  
pp. 174-180
Author(s):  
Poonam Sharma ◽  
Ashwani Kumar Dubey ◽  
Ayush Goyal

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.


Author(s):  
Srinivasan A ◽  
Sudha S

One of the main causes of blindness is diabetic retinopathy (DR) and it may affect people of any ages. In these days, both young and old ages are affected by diabetes, and the di abetes is the main cause of DR. Hence, it is necessary to have an automated system with good accuracy and less computation time to diagnose and treat DR, and the automated system can simplify the work of ophthalmologists. The objective is to present an overview of various works recently in detecting and segmenting the various lesions of DR. Papers were categorized based on the diagnosing tools and the methods used for detecting early and advanced stage lesions. The early lesions of DR are microaneurysms, hemorrhages, exudates, and cotton wool spots and in the advanced stage, new and fragile blood vessels can be grown. Results have been evaluated in terms of sensitivity, specificity, accuracy and receiver operating characteristic curve. This paper analyzed the various steps and different algorithms used recently for the detection and classification of DR lesions. A comparison of performances has been made in terms of sensitivity, specificity, area under the curve, and accuracy. Suggestions, future workand the area to be improved were also discussed.Keywords: Diabetic retinopathy, Image processing, Morphological operations, Neural network, Fuzzy logic. 


Sensors ◽  
2018 ◽  
Vol 18 (11) ◽  
pp. 3742 ◽  
Author(s):  
Alessandro Simeone ◽  
Bin Deng ◽  
Nicholas Watson ◽  
Elliot Woolley

Clean-in-place (CIP) processes are extensively used to clean industrial equipment without the need for disassembly. In food manufacturing, cleaning can account for up to 70% of water use and is also a heavy user of energy and chemicals. Due to a current lack of real-time in-process monitoring, the non-optimal control of the cleaning process parameters and durations result in excessive resource consumption and periods of non-productivity. In this paper, an optical monitoring system is designed and realized to assess the amount of fouling material remaining in process tanks, and to predict the required cleaning time. An experimental campaign of CIP tests was carried out utilizing white chocolate as fouling medium. During the experiments, an image acquisition system endowed with a digital camera and ultraviolet light source was employed to collect digital images from the process tank. Diverse image segmentation techniques were considered to develop an image processing procedure with the aim of assessing the area of surface fouling and the fouling volume throughout the cleaning process. An intelligent decision-making support system utilizing nonlinear autoregressive models with exogenous inputs (NARX) Neural Network was configured, trained and tested to predict the cleaning time based on the image processing results. Results are discussed in terms of prediction accuracy and a comparative study on computation time against different image resolutions is reported. The potential benefits of the system for resource and time efficiency in food manufacturing are highlighted.


2018 ◽  
Vol 27 (10) ◽  
pp. 1850158 ◽  
Author(s):  
Rekha Yadav ◽  
Pawan Kumar Dahiya ◽  
Rajesh Mishra

In this paper, a novel method to realize LC Voltage-Controlled-Oscillator (LC-VCO) operating at 76.2–76.7[Formula: see text]GHz frequency band for microwave RFIC component is presented. The model of cross-coupled differential LC-VCO is designed in 45[Formula: see text]nm technology using Complementary Metal Oxide Semiconductor (CMOS) process for Frequency Modulated Carrier Wave (FMCW) automotive radar sensors and RF transceivers application. The impact of VDD, control voltage and temperature variation on frequency shift, phase noise, and output power has been analyzed to optimize the trade-off between frequency, phase noise, and power requirement. The results depict that LC-VCO dissipates 10.45[Formula: see text]mW power at an operating voltage of 1.5[Formula: see text]V. The phase noise has been observed to be [Formula: see text]90[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset at 76[Formula: see text]GHz carrier frequency. The estimated layout area of IC is [Formula: see text]m2. The result shows the edge of the design over existing techniques.


2019 ◽  
Vol 43 (7) ◽  
Author(s):  
A. Glory Sujitha ◽  
Dr. P. Vasuki ◽  
A. Amala Deepan
Keyword(s):  

2019 ◽  
Vol 29 (08) ◽  
pp. 2050130 ◽  
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.


1990 ◽  
Vol 28 (4) ◽  
pp. 735-737 ◽  
Author(s):  
Li Wang ◽  
Dong-chen He ◽  
A. Fabbri
Keyword(s):  

Author(s):  
Valentina Boccia ◽  
Alfredo Renga ◽  
Giancarlo Rufino ◽  
Antonio Moccia ◽  
Marco D'Errico ◽  
...  
Keyword(s):  

Author(s):  
Tran Van Hoi ◽  
Ngo Thi Lanh ◽  
Nguyen Xuan Truong ◽  
Nguyen Huu Duc ◽  
Bach Gia Duong

<p>This paper focuses on the design and implementation of a front-end for a Vinasat satellite receiver with auto-searching mechanism and auto-tracking satellite. The front-end consists of a C-band low-noise block down-converter and a L-band receiver. The receiver is designed to meet the requirements about wide-band, high sensitivity, large dynamic range, low noise figure. To reduce noise figure and increase bandwidth, the C-band low-noise amplifier is designed using T-type of matching network with negative feedback and the L-band LNA is designed using cascoded techniques. The local oscillator uses a voltage controlled oscillator combine phase locked loop to reduce the phase noise and select channels. The front-end has successfully been designed and fabricated with parameters: Input frequency is C-band; sensitivity is greater than -130 dBm for C-band receiver and is greater than -110dBm for L-band receiver; output signals are AM/FM demodulation, I/Q demodulation, baseband signals.</p>


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