scholarly journals Elliptic-Curve Crypto Processor for RFID Applications

2021 ◽  
Vol 11 (15) ◽  
pp. 7079
Author(s):  
Muhammad Rashid ◽  
Sajjad Shaukat Jamal ◽  
Sikandar Zulqarnain Khan ◽  
Adel R. Alharbi ◽  
Amer Aljaedi ◽  
...  
Keyword(s):  
Elliptic Curve ◽  
Radio Frequency Identification ◽  
Initial Point ◽  
Building Blocks ◽  
Low Latency ◽  
Clock Frequency ◽  
Low Area ◽  
Field Programmable ◽  
Frequency Identification ◽  
Rfid Applications

This work presents an Elliptic-curve Point Multiplication (ECP) architecture with a focus on low latency and low area for radio-frequency-identification (RFID) applications over GF(2163). To achieve low latency, we have reduced the clock cycles by using: (i) three-shift buffers in the datapath to load Elliptic-curve parameters as well as an initial point, (ii) the identical size of input/output interfaces in all building blocks of the architecture. The low area is preserved by using the same hardware resources of squaring and multiplication for inversion computation. Finally, an efficient controller is used to control the inferred logic. The proposed ECP architecture is modeled in Verilog and the synthesis results are given on three different 7-series FPGA (Field Programmable Gate Array) devices, i.e., Kintex-7, Artix-7, and Virtex-7. The performance of the architecture is provided with the integration of a schoolbook multiplier (implemented with two different logic styles, i.e., combinational and sequential). On Kintex-7, the combinational implementation style of a schoolbook multiplier results in power-optimized, i.e., 161 μW, values with an expense of (i) hardware resources, i.e., 3561 look-up-tables and 1527 flip-flops, (ii) clock frequency, i.e., 227 MHz, and (iii) latency, i.e., 11.57 μs. On the same Kintex-7 device, the sequential implementation style of a schoolbook multiplier provides, (i) 2.88 μs latency, (ii) 1786 look-up-tables and 1855 flip-flops, (iii) 647 μW power, and (iv) 909 MHz clock frequency. Therefore, the reported area, latency and power results make the proposed ECP architecture well-suited for RFID applications.

scholarly journals A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2698
Author(s):  
Muhammad Rashid ◽  
Mohammad Mazyad Hazzazi  ◽  
Sikandar Zulqarnain Khan ◽  
Adel R. Alharbi  ◽  
Asher Sajid  ◽  
...  
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
State Of The Art ◽  
Critical Path ◽  
Clock Frequency ◽  
Description Language ◽  
Point Multiplication ◽  
Low Area ◽  
Field Programmable ◽  
Hardware Description

This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over GF(2163) with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over GF(2163) is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 μs for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 μW) and Kintex-7 (61 μW) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.

scholarly journals Compact Tri-band Bandpass Filter Based on Asymmetric Step Impedance Resonators for WiMAX and RFID Systems

2021 ◽  
Vol 21 (4) ◽  
pp. 316-321
Author(s):  
Abdul Basit ◽  
Muhammad Irfan Khattak ◽  
Ayman Althuwayb ◽  
Jamel Nebhen
Keyword(s):  
Radio Frequency Identification ◽  
Bandpass Filter ◽  
Coupled Resonators ◽  
Simple Method ◽  
Rfid Systems ◽  
Fundamental Frequencies ◽  
Half Wavelength ◽  
Frequency Identification ◽  
One Step ◽  
Rfid Applications

In this article, a simple method is developed to design a highly miniaturized tri-band bandpass filter (BPF) utilizing two asymmetric coupled resonators with one step discontinuity and one uniform impedance resonator (UIR) for worldwide interoperability for microwave access (WiMAX) and radio frequency identification (RFID) applications. The first and second passbands located at 3.7 GHz and 6.6 GHz are achieved through two asymmetric coupled step impedance resonators (SIRs), while the third passband, centered at 9 GHz, is achieved using a half-wavelength UIR, respectively. The fundamental frequencies of this BPF are implemented by tuning the physical length ratio (α) and impedance ratio (R) of the asymmetric SIRs. The proposed filter is designed and fabricated with a circuit dimension of 13.69 mm × 25 mm (0.02 λg × 0.03 λg), where λg represents the guided wavelength at the first passband. The experimental and measured results are provided with good matching.

scholarly journals Dual-Band Monopole Antenna for RFID Applications

2019 ◽  
Vol 11 (2) ◽  
pp. 31 ◽  
Author(s):  
Naser Ojaroudi Parchin ◽  
Haleh Jahanbakhsh Basherlou ◽  
Raed Abd-Alhameed ◽  
James Noras
Keyword(s):  
Radio Frequency Identification ◽  
Monopole Antenna ◽  
Dual Band ◽  
Rfid Technology ◽  
Antenna Structure ◽  
The Past ◽  
Frequency Identification ◽  
Rfid Applications ◽  
Significant Attention ◽  
Good Agreement

Over the past decade, radio-frequency identification (RFID) technology has attracted significant attention and become very popular in different applications, such as identification, management, and monitoring. In this study, a dual-band microstrip-fed monopole antenna has been introduced for RFID applications. The antenna is designed to work at the frequency ranges of 2.2–2.6 GHz and 5.3–6.8 GHz, covering 2.4/5.8 GHz RFID operation bands. The antenna structure is like a modified F-shaped radiator. It is printed on an FR-4 dielectric with an overall size of 38 × 45 × 1.6 mm3. Fundamental characteristics of the antenna in terms of return loss, Smith Chart, phase, radiation pattern, and antenna gain are investigated and good results are obtained. Simulations have been carried out using computer simulation technology (CST) software. A prototype of the antenna was fabricated and its characteristics were measured. The measured results show good agreement with simulations. The structure of the antenna is planar, simple to design and fabricate, easy to integrate with RF circuit, and suitable for use in RFID systems.

scholarly journals Time-Efficient Cloning Attacks Identification in Large-Scale RFID Systems

2017 ◽  
Vol 2017 ◽  
pp. 1-9 ◽  
Author(s):  
Ju-min Zhao ◽  
Ding Feng ◽  
Deng-ao Li ◽  
Wei Gong ◽  
Hao-xiang Liu ◽  
...  
Keyword(s):  
Radio Frequency ◽  
Radio Frequency Identification ◽  
Large Scale ◽  
Emerging Technology ◽  
Current Form ◽  
Rfid Systems ◽  
Frequency Identification ◽  
Rfid Applications

Radio Frequency Identification (RFID) is an emerging technology for electronic labeling of objects for the purpose of automatically identifying, categorizing, locating, and tracking the objects. But in their current form RFID systems are susceptible to cloning attacks that seriously threaten RFID applications but are hard to prevent. Existing protocols aimed at detecting whether there are cloning attacks in single-reader RFID systems. In this paper, we investigate the cloning attacks identification in the multireader scenario and first propose a time-efficient protocol, called the time-efficient Cloning Attacks Identification Protocol (CAIP) to identify all cloned tags in multireaders RFID systems. We evaluate the performance of CAIP through extensive simulations. The results show that CAIP can identify all the cloned tags in large-scale RFID systems fairly fast with required accuracy.

Circularly polarized square slot microstrip antenna for RFID applications

2015 ◽  
Vol 8 (8) ◽  
pp. 1237-1242 ◽  
Author(s):  
Neha Sharma ◽  
Anil Kumar Gautam ◽  
Binod Kumar Kanaujia
Keyword(s):  
Radio Frequency Identification ◽  
Microstrip Antenna ◽  
Axial Ratio ◽  
Slot Antenna ◽  
Circularly Polarized ◽  
Broad Bandwidth ◽  
Antenna Performance ◽  
Frequency Identification ◽  
Rfid Applications ◽  
Good Agreement

In this paper, a novel circularly polarized square slot microstrip antenna is proposed for radio frequency identification (RFID) applications. The circular polarization is achieved by incorporating an arc-shaped strip in the square slot antenna. This antenna is fed by deformed bent feeding line to achieve a broad bandwidth (BW). The key parameters of the antenna are used for parametric study to understand the influence on the antenna performance. To validate simulation results of the design, a prototype is fabricated on the commercially available FR4 material. Measured results show a good agreement with the simulated results. It is found that the antenna shows an impedance BW of 170 MHz (844–1014 MHz) and axial-ratio BW of 170 MHz (834–1004 MHz), which shows that the proposed antenna is a good candidate to be used as a RFID antenna.

scholarly journals Microruban Dipole Antenna for RFID Applications at 2.45 GHz

2016 ◽  
Vol 6 (6) ◽  
pp. 2891 ◽  
Author(s):  
Loubna Berrich ◽  
Lahbib Zenkouar
Keyword(s):  
Radio Frequency Identification ◽  
Integrated Circuit ◽  
Input Impedance ◽  
Dipole Antenna ◽  
Antenna Design ◽  
Reflection Coefficients ◽  
Ansoft Hfss ◽  
Frequency Identification ◽  
Folded Dipole ◽  
Rfid Applications

<p><span lang="EN-US">Radio Frequency Identification (RFID) is a technology used mainly to identify tagged items or to track their locations. The most used antennas for RFID application are planar dipoles. For antenna design, it is necessary that the antenna has an impedance value equal to the conjugate of the impedance of the integrated circuit CI. To have a good adaptation allowing the maximum power transfer, there are several techniques. In this work we focus to the adaptation technical T-match which is based on the insertion of a second folded dipole in the center of the first dipole. This technique is modeled by an equivalent circuit to calculate the size of the folded dipole to have new input impedance of the antenna equal to the conjugate of the impedance of the IC. We also look to present a conceptual and technological approach of new topologies of linear dipoles. We proceeded to fold at right angles of the radiating strands in order to explore other topologiesof type  L and Z. The interest of this microstrip folded dipole is their effectiveness to achieve coverage of Blind directions. The results obtained by the platform Ansoft HFSS, allowed us to obtain a quasi-uniform radiation patterns and the reflection coefficients that exceed -37 dB.</span></p>

scholarly journals RFID Security : Tiny Encryption Algorithm And Authentication Protocols

2021 ◽  
Author(s):  
Shirley. Gilbert
Keyword(s):  
Radio Frequency Identification ◽  
Encryption Algorithm ◽  
Performance Potential ◽  
Rfid Tag ◽  
Rf Communication ◽  
Encryption And Decryption ◽  
Field Programmable ◽  
Frequency Identification ◽  
Memory Power ◽  
And Performance

With recent advancement in Radio Frequency Identification (RFID) technology, in addition to reduction in cost of each unit, security has emerged as a major concern. Since an RFID tag has limited resources like memory, power and processing capabilities, authentication must be provided by encryption and decryption procedures that are lightweight consuming minimal resources. This report investigates some relevant RFID encryption algorithms and their possible implementations with respect to security, cost and performance. A survey and brief comparison of the algorithms are performed and the Tiny Encryption Algorithm (TEA) is selected as a feasible solution for encryption and decryption with an acceptable level of security. TEA is implemented on an FPGA (Field Programmable Gate Array) platform. After investigating several state-of-the-art authentication approaches, two protocols are designed incorporating TEA and implemented using VHDL. Simulations corroborate the functionality of the protocols and the two techniques are compared in terms of timing, cost, security and performance. Potential improvements to enhance the security and strengthen RF communication during authentication are explored.

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