scholarly journals Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques

2021 ◽  
Vol 11 (7) ◽  
pp. 3271
Author(s):  
Antonio Lopez-Martin ◽  
Maria Pilar Garde ◽  
Jose M. Algueta-Miguel ◽  
Javier Beloso-Legarra ◽  
Ramon G. Carvajal ◽  
...  
Keyword(s):  
Energy Efficiency ◽  
Energy Efficient ◽  
Low Voltage ◽  
Floating Gate ◽  
Large Signal ◽  
Ultra Low Power ◽  
Class Ab ◽  
Wireless Applications ◽  
Measurement Results ◽  
Prototype Measurement

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage, energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example, including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage, ultra-low-power amplifiers can be designed, preserving, at the same time, excellent small-signal and large-signal performance.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

scholarly journals ENERGY EFFICIENCY IN RESIDENTIAL BUILDINGS, LESS STRAIGHT FORWARD THEN PRESUMED

2018 ◽  
Vol 13 (1) ◽  
Author(s):  
Hugo Hens
Keyword(s):  
Energy Efficiency ◽  
Energy Efficient ◽  
Energy Use ◽  
Low Voltage ◽  
Residential Buildings ◽  
Primary Energy ◽  
Heating And Cooling ◽  
Net Zero ◽  
Energy Conserving ◽  
New Construction

Since the 1990s, the successive EU directives and related national or regional legislations require new construction and retrofits to be as much as possible energy-efficient. Several measures that should stepwise minimize the primary energy use for heating and cooling have become mandated as requirement. However, in reality, related predicted savings are not seen in practice. Two effects are responsible for that. The first one refers to dweller habits, which are more energy-conserving than the calculation tools presume. In fact, while in non-energy-efficient ones, habits on average result in up to a 50% lower end energy use for heating than predicted. That percentage drops to zero or it even turns negative in extremely energy-efficient residences. The second effect refers to problems with low-voltage distribution grids not designed to transport the peaks in electricity whensunny in summer. Through that, a part of converters has to be uncoupled now and then, which means less renewable electricity. This is illustrated by examples that in theory should be net-zero buildings due to the measures applied and the presence of enough photovoltaic cells (PV) on each roof. We can conclude that mandating extreme energy efficiency far beyond the present total optimum value for residential buildings looks questionable as a policy. However, despite that, governments and administrations still seem to require even more extreme measurements regarding energy efficiency.

Novel Ultra-Low-Power Class AB CCII+ Based on Floating-Gate Folded Cascode OTA

2011 ◽  
Vol 31 (2) ◽  
pp. 447-464 ◽  
Author(s):  
Fabian Khateb ◽  
Nabhan Khatib ◽  
David Kubánek
Keyword(s):  
Low Power ◽  
Floating Gate ◽  
Ultra Low Power ◽  
Class Ab ◽  
Folded Cascode ◽  
Power Class

scholarly journals Exploiting Data-dependencies in Ultra Low-power DSP Arithmetic

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 349-363
Author(s):  
V. A. Bartlett ◽  
E. Grass
Keyword(s):  
Energy Efficiency ◽  
Energy Consumption ◽  
Low Power ◽  
Energy Efficient ◽  
Dynamic Logic ◽  
Low Power Consumption ◽  
Ultra Low Power ◽  
Data Dependencies ◽  
Simulation Results ◽  
Asynchronous Environments

Strategies for the design of ultra low power multipliers and multiplier-accumulators are reported. These are optimized for asynchronous applications being able to take advantage of data-dependent computation times. Nevertheless, the low power consumption can be obtained in both synchronous and asynchronous environments. Central to the energy efficiency is a dynamic-logic technique termed Conditional Evaluation which is able to exploit redundancies within the carry-save array and deliver energy consumption which is also heavily data-dependent.Energy efficient adaptations for handling two's complement operands are introduced. Area overheads of the proposed designs are estimated and transistor level simulation results of signed and unsigned multipliers as well as a signed multiplier-accumulator are given.Normalized comparisons with other designs show our approach to use less energy than other published multipliers.

EXTREMELY SCALABLE CROSS-POINT TOP-GATED HETEROJUNCTION TUNNELING-TRANSISTORS

2011 ◽  
Vol 20 (03) ◽  
pp. 707-711
Author(s):  
OSAMA M. NAYFEH ◽  
MADAN DUBEY
Keyword(s):  
Energy Efficiency ◽  
Energy Efficient ◽  
Low Voltage ◽  
Switching Behavior ◽  
Gate Length ◽  
Energy Bands ◽  
Cross Point ◽  
Point Configuration ◽  
Low Voltage Operation ◽  
Tunneling Distance

Energy efficient hetero-junction tunneling transistors in a simple "cross-point" configuration that utilizes top gates are analyzed for use at extremely scaled sub-10 nm gate-lengths. The active tunneling region comprises of a vertical p ++/ n + heterojunction (for example formed at the cross point of p ++ SiGe / n + Si ), where modulation of the energy-bands in the gated n + Si region with a top-gate is used to control the degree of band overlap and tunneling distance and hence current. The sub-threshold swing characteristic of these devices is shown to be potentially highly immune to extreme downscaling to 6 nm gate length allowing for an intact and efficient switching behavior to be retained. The extreme scalability and ultra-low voltage operation could make such cross-point devices useful for alternative applications and architectures that require ultimate energy efficiency.

A Class-AB Bulk-Driven Amplifier with Enhanced Transconductance Using Quasi-Floating Gate Method

2018 ◽  
Vol 27 (09) ◽  
pp. 1850137
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Cmos Technology ◽  
Floating Gate ◽  
Common Source ◽  
Slew Rate ◽  
Power Budget ◽  
Ultra Low Power ◽  
Class Ab ◽  
Flipped Voltage Follower ◽  
Voltage Follower ◽  
Adaptive Biasing

This paper presents a supper class-AB adaptive biasing bulk-driven amplifier for ultra-low-power applications. In the proposed structure, two bulk-driven flipped voltage follower (FVF) cells are reconfigured as nonlinear tail currents using quasi-floating gate method to enhance transconductance and slew rate. In addition, two idle current controllers are employed as common source amplifiers to provide a supper class-AB structure without increasing total current consumption. The proposed structure is simulated in 0.18-[Formula: see text]m CMOS technology at 0.5[Formula: see text]V supply with 35[Formula: see text]nW power budget. The results show a 57.9[Formula: see text]dB DC gain, 8.8[Formula: see text]kHz gain bandwidth and 38.2[Formula: see text]V/ms slew rate for the proposed amplifier.

Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD

2017 ◽  
Vol 27 (03) ◽  
pp. 1850046 ◽  
Author(s):  
Sadulla Shaik ◽  
K. Sri Rama Krishna ◽  
Ramesh Vaddi
Keyword(s):  
Energy Efficiency ◽  
Energy Efficient ◽  
Low Voltage ◽  
Field Effect Transistors ◽  
Full Adder ◽  
Cmos Technology ◽  
Logic Design ◽  
Transmission Gate ◽  
Reliability Characteristics ◽  
Efficient Option

Tunnel field-effect transistors (TFETs) as low voltage device options have attracted recent attention for energy efficient circuit designs with CMOS technology scaling. This paper presents the circuit and architectural co-design approach for designing reliable and energy efficient architectures (adder cells) for new computing platforms at supply voltages. At circuit level TFET-based 28-transistor static logic design (28T) and 24-transistor transmission gate logic design (24T) have been explored. At architectural level, multiplexer (MUX)-based 22-transistor full adder design (22T) is proposed. Performance of TFET-based architectures have also been benchmarked with 20[Formula: see text]nm double gate Si FinFET technology. It has been seen that with FinFET technology 24T design is not effective in terms of energy efficiency and reliability (due to the large leakage currents in transmission gate logic topology). 28T design is the best in reliability perspective (in terms of reduced over shoots, full logic swing and reduced glitch duration etc.) and 22T design to be energy efficient option. It has been demonstrated in this paper that TFET’s steep slope characteristics enable the 24T design to have similar reliability characteristics like 28T design and energy efficiency like 22T design. TFET-based 22T design has [Formula: see text]91% smaller energy delay product (EDP) and [Formula: see text]84.4% less power delay product (PDP) in comparison to the low threshold voltage (LVT) FinFET 22T design at 0.2[Formula: see text]V VDD.

scholarly journals Performance Evaluation of Publish-Subscribe Systems in IoT Using Energy-Efficient and Context-Aware Secure Messages

2021 ◽  
Author(s):  
Norisvaldo Ferraz Junior ◽  
Anderson AA Silva ◽  
Adilson E Guelfi ◽  
Sergio T Kofuji
Keyword(s):  
Energy Efficiency ◽  
Performance Evaluation ◽  
Energy Efficient ◽  
High Capacity ◽  
Context Aware ◽  
Cloud Platform ◽  
Ultra Low Power ◽  
Message Structure ◽  
End To End ◽  
Iot Devices

Abstract Background: The Internet of Things (IoT) enables the development of innovative applications in various domains such as healthcare, transportation, and Industry 4.0. Publish-subscribe systems enable IoT devices to communicate with the cloud platform. However, IoT applications need context-aware messages to translate the data into contextual information, allowing the applications to act cognitively. Besides, end-to-end security of publish-subscribe messages on both ends (devices and cloud) is essential. However, achieving security on constrained IoT devices with memory, payload, and energy restrictions is a challenge. Contribution: Messages in IoT need to achieve both energy efficiency and secure delivery. Thus, the main contribution of this paper refers to a performance evaluation of a message structure that standardizes the publish-subscribe topic and payload used by the cloud platform and the IoT devices. We also propose a standardization for the topic and payload for publish-subscribe systems. Conclusion: The messages promote energy efficiency, enabling ultra-low-power and high-capacity devices and reducing the bytes transmitted in the IoT domain. The performance evaluation demonstrates that publish-subscribe systems (namely, AMQP, DDS, and MQTT) can use our proposed energy-efficient message structure on IoT. Additionally, the message system provides end-to-end confidentiality, integrity, and authenticity between IoT devices and the cloud platform.

Sign in / Sign up

Export Citation Format

Share Document