scholarly journals Characterization and Optimal Design of Silicon-Rich Nitride Nonlinear Waveguides for 2 μm Wavelength Band

2020 ◽  
Vol 10 (22) ◽  
pp. 8087
Author(s):  
Zhihua Tu ◽  
Daru Chen ◽  
Hao Hu ◽  
Shiming Gao ◽  
Xiaowei Guan
Keyword(s):  
Optical Communication ◽  
High Performance ◽  
Figure Of Merit ◽  
Continuous Wave ◽  
Design Method ◽  
Wavelength Band ◽  
Nonlinear Waveguides ◽  
Long Wavelength ◽  
Ridge Waveguides ◽  
On Chip

Optical communication using the 2 μm wavelength band is attracting growing attention for the sake of mitigating the information ‘capacity crunch’ on the way, where on-chip nonlinear waveguides can play vital roles. Here, silicon-rich nitride (SRN) ridge waveguides with different widths and rib heights are fabricated and measured. Linear characterizations show a loss of ~2 dB/cm of the SRN ridge waveguides and four-wave mixing (FWM) experiments with a continuous wave (CW) pump reveal a nonlinear refractive index of ~1.13 × 10−18 m2/W of the SRN material around the wavelength 1950 nm. With the extracted parameters, dimensions of the SRN ridge waveguides are optimally designed for improved nonlinear performances for the 2 μm band, i.e., a maximal nonlinear figure of merit (i.e., the ratio of nonlinearity to loss) of 0.0804 W−1 or a super-broad FWM bandwidth of 518 nm. Our results and design method open up new possibilities for achieving high-performance on-chip nonlinear waveguides for long-wavelength optical communications.

scholarly journals Biomimicry-Gradient-Based Algorithm as Applied to Photonic Devices Design: Inverse Design of Flat Plasmonic Metalenses

2021 ◽  
Vol 11 (12) ◽  
pp. 5436
Author(s):  
Kofi Edee
Keyword(s):  
High Performance ◽  
Figure Of Merit ◽  
Initial Conditions ◽  
Design Method ◽  
Optimal Solution ◽  
High Energy ◽  
Inverse Design ◽  
Design Parameters ◽  
Geometrical Parameters ◽  
Efficient Design

The classical adjoint-based topology optimization (TO) method, based on the use of a random continuous dielectric function as design variable distribution is known to be one of the timely efficient and fast optimization methods enable a very high performance functional optical devices. It relies on the computation of the gradient of a figure of merit (FOM) with respect to the design parameters. The gradient of the figure of merit (FOM) may then be used to update the design vector element in several senarios. One of the most common use scenarios consists of updating simultaneously all the design parameter vector elements. In a linear problem case involving a simply convex FOM-function shape, using the gradient information, it is a relatively easy to reach an optimal solution. In the case of constrained and non linear problems stated in an infinite and indeterminate design space, the conventional TO, a local optimizer, may require multiple restarts, with multiple initial points and multiple runs. The algorithm strongly depends on the initial conditions. In this paper, we report a global-like optimizer inspired by a wolf pack hunting, enabling efficient design of metasurfaces through their geometrical parameters. We apply the method to design a non periodic metasurface consisting of plasmonic metalenses, enabling a high energy flow focusing on a well-defined 2D focus spot. Numerical results show that the proposed inverse design method has a low sensitivity to initial conditions. In our design method of metalens, we optimize the full micro device at once, and demonstrate that the proposed method may provide both symmetric and more creative unexpected asymmetric on-axis metalenses even though under a normal illumination.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

Design and simulation of high performance router on chip based on random routing

2014 ◽  
Vol 27 (7) ◽  
pp. 669-675 ◽  
Author(s):  
Feng Yue ◽  
Runfeng Li ◽  
Tian Chen ◽  
Jun Liu ◽  
Peng Chen ◽  
...  
Keyword(s):  
High Performance ◽  
On Chip

МЕТОДЫ ДОСТИЖЕНИЯ МАКСИМАЛЬНОЙ ЭФФЕКТИВНОСТИ ПЛАТФОРМЫ ПРОТОТИПИРОВАНИЯ ВЫСОКОПРОИЗВОДИТЕЛЬНЫХ СИСТЕМ НА КРИСТАЛЛЕ НА ЗАДАЧАХ ИСКУССТВЕННОГО ИНТЕЛЛЕКТА

2020 ◽  
Vol 96 (3s) ◽  
pp. 585-588
Author(s):  
С.Е. Фролова ◽  
Е.С. Янакова
Keyword(s):  
Neural Network ◽  
Artificial Intelligence ◽  
Computer Vision ◽  
High Performance ◽  
Systems On Chip ◽  
High Performance Systems ◽  
On Chip ◽  
Network Technologies ◽  
Neural Network Technologies

Предлагаются методы построения платформ прототипирования высокопроизводительных систем на кристалле для задач искусственного интеллекта. Изложены требования к платформам подобного класса и принципы изменения проекта СнК для имплементации в прототип. Рассматриваются методы отладки проектов на платформе прототипирования. Приведены результаты работ алгоритмов компьютерного зрения с использованием нейросетевых технологий на FPGA-прототипе семантических ядер ELcore. Methods have been proposed for building prototyping platforms for high-performance systems-on-chip for artificial intelligence tasks. The requirements for platforms of this class and the principles for changing the design of the SoC for implementation in the prototype have been described as well as methods of debugging projects on the prototyping platform. The results of the work of computer vision algorithms using neural network technologies on the FPGA prototype of the ELcore semantic cores have been presented.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals Graphene Nanoribbon Gap Waveguides for Dispersionless and Low-Loss Propagation with Deep-Subwavelength Confinement

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1302
Author(s):  
Zhiyong Wu ◽  
Lei Zhang ◽  
Tingyin Ning ◽  
Hong Su ◽  
Irene Ling Li ◽  
...  
Keyword(s):  
High Performance ◽  
Chemical Potential ◽  
Shape Change ◽  
Optical Switch ◽  
Pulse Amplitude ◽  
Propagation Distance ◽  
Graphene Nanoribbon ◽  
Low Loss ◽  
High Loss ◽  
On Chip

Surface plasmon polaritons (SPPs) have been attracting considerable attention owing to their unique capabilities of manipulating light. However, the intractable dispersion and high loss are two major obstacles for attaining high-performance plasmonic devices. Here, a graphene nanoribbon gap waveguide (GNRGW) is proposed for guiding dispersionless gap SPPs (GSPPs) with deep-subwavelength confinement and low loss. An analytical model is developed to analyze the GSPPs, in which a reflection phase shift is employed to successfully deal with the influence caused by the boundaries of the graphene nanoribbon (GNR). It is demonstrated that a pulse with a 4 μm bandwidth and a 10 nm mode width can propagate in the linear passive system without waveform distortion, which is very robust against the shape change of the GNR. The decrease in the pulse amplitude is only 10% for a propagation distance of 1 μm. Furthermore, an array consisting of several GNRGWs is employed as a multichannel optical switch. When the separation is larger than 40 nm, each channel can be controlled independently by tuning the chemical potential of the corresponding GNR. The proposed GNRGW may raise great interest in studying dispersionless and low-loss nanophotonic devices, with potential applications in the distortionless transmission of nanoscale signals, electro-optic nanocircuits, and high-density on-chip communications.

scholarly journals Self-Healing Router Approach for High-Performance Network-on-Chip

2021 ◽  
Vol 2 ◽  
pp. 485-496
Author(s):  
Kasem Khalil ◽  
Omar Eldash ◽  
Ashok Kumar ◽  
Magdy Bayoumi
Keyword(s):  
High Performance ◽  
Network On Chip ◽  
Self Healing ◽  
On Chip

scholarly journals Facile fabrication of graphene-based high-performance microsupercapacitors operating at high temperature of 150 oC

2021 ◽  
Author(s):  
Viktoriia Mishukova ◽  
Nicolas Boulanger ◽  
Artem Iakunkov ◽  
Szymon Sollami Delekta ◽  
Xiaodong Zhuang ◽  
...  
Keyword(s):  
High Temperature ◽  
Energy Storage ◽  
High Performance ◽  
Electronic Circuits ◽  
Industry Applications ◽  
Facile Fabrication ◽  
On Chip

Many industry applications require electronic circuits and systems to operate at high temperature over 150 oC. Although planar microsupercapacitors (MSCs) have great potential for miniaturized on-chip integrated energy storage components,...

scholarly journals A Brief Overview of On-Chip Voltage Regulation in High-Performance and High-Density Integrated Circuits

IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 813-826
Author(s):  
Farid Uddin Ahmed ◽  
Zarin Tasnim Sandhie ◽  
Liaquat Ali ◽  
Masud H. Chowdhury
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Voltage Regulation ◽  
High Density ◽  
On Chip

Sputtered titanium nitride films with finely tailored surface activity and porosity for high performance on-chip micro-supercapacitors

2021 ◽  
Vol 489 ◽  
pp. 229406
Author(s):  
Nana Sun ◽  
Dayu Zhou ◽  
Wenwen Liu ◽  
Aikui Li ◽  
Yunpeng Su ◽  
...  
Keyword(s):  
Titanium Nitride ◽  
Surface Activity ◽  
High Performance ◽  
On Chip
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