scholarly journals Analysis of Work-Function Variation Effects in a Tunnel Field-Effect Transistor Depending on the Device Structure

2020 ◽  
Vol 10 (15) ◽  
pp. 5378
Author(s):  
Garam Kim ◽  
Jang Hyun Kim ◽  
Jaemin Kim ◽  
Sangwan Kim
Keyword(s):  
Work Function ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Tunneling Current ◽  
Deposition Process ◽  
Device Structure ◽  
Metal Gates ◽  
Grain Distribution ◽  
Aided Design

Metal gate technology is one of the most important methods used to increase the low on-current of tunnel field-effect transistors (TFETs). However, metal gates have different work-functions for each grain during the deposition process, resulting in work-function variation (WFV) effects, which means that the electrical characteristics vary from device to device. The WFV of a planar TFET, double-gate (DG) TFET, and electron-hole bilayer TFET (EHBTFET) were examined by technology computer-aided design (TCAD) simulations to analyze the influences of device structure and to find strategies for suppressing the WFV effects in TFET. Comparing the WFV effects through the turn-on voltage (Vturn-on) distribution, the planar TFET showed the largest standard deviation (σVturn-on) of 20.1 mV, and it was reduced by −26.4% for the DG TFET and −80.1% for the EHBTFET. Based on the analyses regarding metal grain distribution and energy band diagrams, the WFV of TFETs was determined by the number of metal grains involved in the tunneling current. Therefore, the EHBTFET, which can determine the tunneling current by all of the metal grains where the main gate and the sub gate overlap, is considered to be a promising structure that can reduce the WFV effect of TFETs.

scholarly journals Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 454
Author(s):  
You Wang ◽  
Yu Mao ◽  
Qizheng Ji ◽  
Ming Yang ◽  
Zhaonian Yang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Field Effect ◽  
Electrostatic Discharge ◽  
Field Effect Transistors ◽  
Test Method ◽  
Current Path ◽  
Simulation Results ◽  
Current Characteristics ◽  
Aided Design

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

Influence of work function variation of metal gates on fluctuation of sub-threshold drain current for fin field-effect transistors with undoped channels

2014 ◽  
Vol 53 (4S) ◽  
pp. 04EC11 ◽  
Author(s):  
Takashi Matsukawa ◽  
Yongxun Liu ◽  
Kazuhiko Endo ◽  
Junichi Tsukada ◽  
Hiromi Yamauchi ◽  
...  
Keyword(s):  
Work Function ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Metal Gates

scholarly journals Random Dopant Fluctuation-Induced Variability in n-Type Junctionless Dual-Metal Gate FinFETs

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 282 ◽  
Author(s):  
Liang Dai ◽  
Weifeng Lü ◽  
Mi Lin
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Voltage ◽  
Metal Gate ◽  
Random Dopant Fluctuation ◽  
Computer Aided ◽  
Dual Metal ◽  
Aided Design ◽  
Random Dopant

We investigate the effect of random dopant fluctuation (RDF)-induced variability in n-type junctionless (JL) dual-metal gate (DMG) fin field-effect transistors (FinFETs) using a 3D computer-aided design simulation. We show that the drain voltage (VDS) has a significant impact on the electrostatic integrity variability caused by RDF and is dependent on the ratio of gate lengths. The RDF-induced variability also increases as the length of control gate near the source decreases. Our simulations suggest that the proportion of the gate metal near the source to the entire gate should be greater than 0.5.

scholarly journals Investigation on the Hump Behavior of Gate-Normal Nanowire Tunnel Field-Effect Transistors (NWTFETs)

2020 ◽  
Vol 10 (24) ◽  
pp. 8880
Author(s):  
Min Woo Kang ◽  
Woo Young Choi
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Three Dimensional ◽  
Gate Insulator ◽  
Radius Of Curvature ◽  
Computer Aided ◽  
Simulation Results ◽  
Tcad Simulation ◽  
Aided Design

The hump behavior of gate-normal nanowire tunnel field-effect transistors (NWTFETs) is investigated by using a three-dimensional technology computer-aided design (TCAD) simulation. The simulation results show that the hump behavior degrades the subthreshold swing (SS) and on-current (Ion) because the corners and sides of nanowires (NWs) have different surface potentials. The hump behavior can be successfully suppressed by increasing the radius of curvature (R) of NWs and reducing gate insulator thickness (Tins).

scholarly journals Analysis of Current Variation with Work Function Variation in L-Shaped Tunnel-Field Effect Transistor

Micromachines ◽  
2020 ◽  
Vol 11 (8) ◽  
pp. 780
Author(s):  
Jang Hyun Kim ◽  
Hyun Woo Kim ◽  
Young Suh Song ◽  
Sangwan Kim ◽  
Garam Kim
Keyword(s):  
Work Function ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Tunnel Barrier ◽  
Entire Area ◽  
Current Variation ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design

In this paper, an investigation is performed to analyze the L-shaped tunnel field-effect transistor (TFET) depending on a gate work function variation (WFV) with help of technology computer-aided design (TCAD) simulation. Depending on the gate voltage, the three variations occur in transfer curves. The first one is the on-state current (ION) variation, the second one is the hump current (IHUMP) variation, and the last one is ambipolar current (IAMB) variation. According to the simulation results, the ION variation is sensitive depending on the size of the tunneling region and could be reduced by increasing the tunneling region. However, the IHUMP and IAMB variations are relatively irrelevant to the size of the tunneling region. In order to analyze the cause of this difference, we investigated the band-to-band tunneling (BTBT) rate according to WFV cases. The results show that when ION is formed in L-shaped TFET, the BTBT rate relies on the WFV in the whole region of the gate because the tunnel barrier is formed in the entire area where the source and the gate meet. On the other hand, when the IHUMP and IAMB are formed in L-shaped TFET, the BTBT rate relies on the WFV in the edge of the gate.

scholarly journals Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Nanomaterials ◽  
2019 ◽  
Vol 9 (2) ◽  
pp. 181 ◽  
Author(s):  
Hongliang Lu ◽  
Bin Lu ◽  
Yuming Zhang ◽  
Yimen Zhang ◽  
Zhijun Lv
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Current Model ◽  
Tunneling Current ◽  
Drain Current ◽  
Device Structure ◽  
Band Engineering ◽  
Novel Device ◽  
Analytical Potential ◽  
Good Agreement

The practical use of tunnel field-effect transistors is retarded by the low on-state current. In this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure of source-pocket concept are combined in a single tunnel field-effect transistor to extensively boost the device performance. The proposed device shows improved tunnel on-state current and subthreshold swing. In addition, analytical potential model for the proposed device is developed and tunneling current is also calculated. Good agreement of the modeled results with numerical simulations verifies the validation of our model. With significantly reduced simulation time while acceptable accuracy, the model would be helpful for the further investigation of TFET-based circuit simulations.

scholarly journals Study of Work-Function Variation on Performance of Dual-Metal Gate Fin Field-Effect Transistor

2020 ◽  
Author(s):  
Tianyu Yu ◽  
Liang Dai ◽  
Zhifeng Zhao ◽  
Weifeng Lyu ◽  
Mi Lin
Keyword(s):  
Work Function ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Gate ◽  
Statistical Fluctuations ◽  
Effect Transistor ◽  
Dual Metal ◽  
Aided Design ◽  
The Impact

The impact of work-function variation (WFV) on performance of an inversion-mode (IM) dual-metal gate (DMG) fin field-effect transistor (FinFET) was investigated for the first time. The statistical fluctuations induced by WFV on the threshold-voltage (VTH), transconductance (gm), and subthreshold slope (SS) were demonstrated and estimated utilizing a 3D technology computer-aided design (TCAD) simulator. We found that the performance variations of the DMG FinFET were affected by two different metals near the drain and near the source, respectively. Additionally, this effect of the two metals on the channel was not monotonic with the length of the channel of their own control. Our work fills a gap in the study of WFV for a DMG IM FinFET and provides a reference for optimizing the distribution of the two metals.

Si1-yGeyor Ge1-zSnzSource/Drain Stressors on Strained Si1-xGex-Channel P-Type Field-Effect Transistors: A Technology Computer-Aided Design Study

2013 ◽  
Vol 52 (4S) ◽  
pp. 04CC01 ◽  
Author(s):  
Geert Eneman ◽  
An De Keersgieter ◽  
Liesbeth Witters ◽  
Jerome Mitard ◽  
Benjamin Vincent ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Design Study ◽  
Computer Aided ◽  
P Type ◽  
Aided Design

scholarly journals A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 164
Author(s):  
Ke Han ◽  
Shanglin Long ◽  
Zhongliang Deng ◽  
Yannan Zhang ◽  
Jiawei Li
Keyword(s):  
Low Power ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Electrical Characteristics ◽  
Source Voltage ◽  
Effect Transistor ◽  
Supply Current ◽  
Aided Design

This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology computer-aided design (TCAD). The GAS GAA TFET contains a combination of around-source germanium and silicon, which have different bandgaps. With an increase in the gate-source voltage, band-to-band tunnelling (BTBT) in silicon rapidly approached saturation since germanium has a higher BTBT probability than silicon. At this moment, germanium could still supply current increment, resulting in a steady and steep average subthreshold swing ( S S AVG ) and a higher ON-state current. The GAS GAA TFET was optimised through work function and drain overlapping engineering. The optimised GAS GAA TFET exhibited a high ON-state current ( I ON ) (11.9 μ A), a low OFF-state current ( I OFF ) ( 2.85 × 10 − 9 μ A), and a low and steady S S AVG (57.29 mV/decade), with the OFF-state current increasing by 10 7 times. The GAS GAA TFET has high potential for use in low-power applications.

Optimizing the Screen-Grid Field Effect Transistor for high drive current and low Miller capacitance

2009 ◽  
Vol 1174 ◽  
Author(s):  
Yasaman Shadrokh ◽  
Kristel Fobelets ◽  
Enrique Velazquez-Perez
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Degrees Of Freedom ◽  
Field Effect Transistors ◽  
Switching Speed ◽  
High Drive ◽  
Gate Control ◽  
Effect Transistor ◽  
Screen Grid ◽  
Aided Design

AbstractReduction of parasitic capacitances and improvement of the on-off current ratio (ION/IOFF) can be achieved by increasing the gate control in Field Effect Transistors (FETs). Multiple gated FETs (MugFETs) lend themselves well for this. The MugFET investigated in this manuscript is the Screen Grid FET (SGrFET) that consists of multiple gate cylinders inside the channel perpendicular to the current flow. In this work we illustrate, using 2D Technology Computer Aided Design (TCAD), that the multiple geometrical degrees of freedom of the SGrFET can be exploited to simultaneously optimise the on-current, ION and the gate-drain Miller parasitic capacitance for increased switching speed.

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