scholarly journals Highly Efficient SCA-Resistant Binary Field Multiplication on 8-Bit AVR Microcontrollers

2020 ◽  
Vol 10 (8) ◽  
pp. 2821
Author(s):  
Seog Chung Seo ◽  
Donggeun Kwon
Keyword(s):  
Performance Improvement ◽  
Power Analysis ◽  
Timing Analysis ◽  
Block Size ◽  
Optimization Techniques ◽  
Binary Field ◽  
Elliptic Curve Cryptosystems ◽  
Xor Operation ◽  
Improved Performance ◽  
Field Multiplication

Binary field ( B F ) multiplication is a basic and important operation for widely used crypto algorithms such as the GHASH function of GCM (Galois/Counter Mode) mode and NIST-compliant binary Elliptic Curve Cryptosystems (ECCs). Recently, Seo et al. proposed a novel SCA-resistant binary field multiplication method in the context of GHASH optimization in AES GCM mode on 8-bit AVR microcontrollers (MCUs). They proposed a concept of Dummy XOR operation with a kind of garbage registers and a concept of instruction level atomicity ( I L A ) for resistance against Timing Analysis (TA) and Simple Power Analysis (SPA) and used a Karatsuba Block-Comb multiplication approach for efficiency. Even though their method achieved a large performance improvement compared with previous works, it still has room for improvement on the 8-bit AVR platform. In this paper, we propose a more improved binary field multiplication method on 8-bit AVR MCUs. Our method basically adopts a Dummy XOR technique using a set of garbage registers for TA and SPA security; however, we save the number of used garbage registers from eight to one by using the fact that the number of used garbage registers does not affect TA and SPA security. In addition, we apply a multiplier encoding approach so as to decrease the number of required registers when accessing the multiplier, which enables the use of extended block size in the Karatsuba Block-Comb multiplication technique. Actually, the proposed technique extends the block size from four to eight and the proposed binary field multiplication method can compute a 128-bit B F multiplication with only 3816 clock cycles ( c c ) (resp. 3490 c c ) with (resp. without) the multiplier encoding process, which is almost a 32.8% (resp. 38.5%) improvement compared with 5675 c c of the best previous work. We apply the proposed technique to the GHASH function of the GCM mode with several additional optimization techniques. The proposed GHASH implementation provides improved performance by over 42% compared with the previous best result. The concept of the proposed B F method can be extended to other MCUs, including 16-bit MSP430 MCUs and 32-bit ARM MCUs.

Consideration of structural constraints in passive rotor blade design for improved performance

2015 ◽  
Vol 119 (1222) ◽  
pp. 1513-1539 ◽  
Author(s):  
J. W. Lim
Keyword(s):  
Performance Improvement ◽  
Rotor Blade ◽  
Parametric Design ◽  
Control Point ◽  
Bending Moment ◽  
Structural Constraints ◽  
Design Variables ◽  
Significant Performance ◽  
Structural Redesign ◽  
Improved Performance

AbstractThis design study applied parameterisation to rotor blade for improved performance. In the design, parametric equations were used to represent blade planform changes over the existing rotor blade model. Design variables included blade twist, sweep, dihedral, and radial control point. Updates to the blade structural properties with changes in the design variables allowed accurate evaluation of performance objectives and realistic structural constraints – blade stability, steady moments (flap bending, chord bending, and torsion), and the high g manoeuvring pitch link loads. Performance improvement was demonstrated with multiple parametric designs. Using a parametric design with advanced aerofoils, the predicted power reduction was 1·0% in hover, 10·0% at μ = 0·30, and 17·0% at μ = 0·40 relative to the baseline UH-60A rotor, but these were obtained with a 35% increase in the steady chord bending moment at μ = 0·30 and a 20% increase in the half peak-to-peak pitch link load during the UH-60A UTTAS manoeuvre Low vibration was maintained for this design. More rigorous design efforts, such as chord tapering and/or structural redesign of the blade cross section, would enlarge the feasible design space and likely provide significant performance improvement.

scholarly journals Design and Performance Improvement of CNTFET Based Content Addressable Memory (CAM) Cells

2019 ◽  
Vol 9 (1) ◽  
pp. 1694-1698
Keyword(s):  
Performance Improvement ◽  
Power Analysis ◽  
Electronic Device ◽  
Digital Processing ◽  
Basic Component ◽  
Content Addressable Memory ◽  
Innovative Methods ◽  
Scaling Down ◽  
And Performance ◽  
Carbon Nano Tube

The scaling down of transistors is of paramount importance to make ICs and devices more portable and efficient. As it is the most basic component of every electronic device, there is need of finding better and innovative methods of transistor characterization. CNTFET has shown the promise and is best suited for today’s faster digital processing units and Memory devices. Here Carbon Nano Tube (CNT) is characterized for its electrical property and then designed a XOR based CAM cell using CNTFET. Both delay and power analysis for the designed CAM is done.

Efficient Lightweight Hardware Structures of Point Multiplication on Binary Edwards Curves for Elliptic Curve Cryptosystems

2019 ◽  
Vol 28 (09) ◽  
pp. 1950149
Author(s):  
Bahram Rashidi ◽  
Mohammad Abedini
Keyword(s):  
High Speed ◽  
Critical Path ◽  
Low Cost ◽  
Path Delay ◽  
Point Multiplication ◽  
Low Area ◽  
Elliptic Curve Cryptosystems ◽  
Edwards Curves ◽  
Special Cases ◽  
Field Multiplication

This paper presents efficient lightweight hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on general and special cases of binary Edwards curves. The complete differential addition formulas have the cost of [Formula: see text] and [Formula: see text] for general and special cases of BECs, respectively, where [Formula: see text] and [Formula: see text] denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of BECs, the structure is implemented based on 3 concurrent multipliers. Also in the special case of BECs, two structures by employing 3 and 2 field multipliers are proposed for achieving the highest degree of parallelization and utilization of resources, respectively. The field multipliers are implemented based on the proposed efficient digit–digit polynomial basis multiplier. Two input operands of the multiplier proceed in digit level. This property leads to reduce hardware consumption and critical path delay. Also, in the structure, based on the change of input digit size from low digit size to high digit size the number of clock cycles and input words are different. Therefore, the multiplier can be flexible for different cryptographic considerations such as low-area and high-speed implementations. The point multiplication computation requires field inversion, therefore, we use a low-cost Extended Euclidean Algorithm (EEA) based inversion for implementation of this field operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX110 FPGA for two fields [Formula: see text] and [Formula: see text] are achieved. The results show improvements in terms of area and efficiency for the proposed structures compared to previous works.

scholarly journals Efficient Implementation of a Crypto Library Using Web Assembly

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1839
Author(s):  
BoSun Park ◽  
JinGyo Song ◽  
Seog Chung Seo
Keyword(s):  
Key Agreement ◽  
Timing Analysis ◽  
Scalar Multiplication ◽  
Message Authentication ◽  
Authentication Code ◽  
Web Based ◽  
Atomic Block ◽  
Data Authentication ◽  
Improved Performance ◽  
Block Based

We implement a cryptographic library using Web Assembly. Web Assembly is expected to show better performance than Javascript. The proposed library provides comprehensive algorithm sets including revised CHAM, Hash Message Authentication Code (HMAC), and ECDH using the NIST P-256 curve to provide confidentiality, data authentication, and key agreement functions. To optimize the performance of revised CHAM in the proposed library, we apply an existing method that is a four-round combining method and additionally propose the precomputation method to CHAM-64/128. The proposed revised CHAM showed an approximate 2.06 times (CHAM-64/128), approximate 2.13 times (CHAM-128/128), and approximate 2.63 times (CHAM-128/256) performance improvement in Web Assembly compared to JavaScript. In addition, CHAM-64/128 applying the precomputation method showed an improved performance by approximately 1.2 times more than the existing CHAM-64/128. For the ECDH using P-256 curve, the naive implementation of ECDH is vulnerable to side-channel attacks (SCA), e.g., simple power analysis (SPA), and timing analysis (TA). Thus, we apply an SPA and TA resistant scalar multiplication method, which is a core operation in ECDH. We present atomic block-based scalar multiplication by revising the previous work. Existing atomic blocks show a performance overhead of 55%, 23%, and 37%, but atomic blocks proposed to use only P=(X,Y,Z) show 18%, 6%, and 11% performance overhead. The proposed Web Assembly-based crypto library provides enhanced performance and resistance against SCA thus, it can be used in various web-based applications.

Performance Improvement of Power Analysis Attacks on AES with Encryption-Related Signals

2012 ◽  
Vol E95.A (6) ◽  
pp. 1091-1094 ◽  
Author(s):  
You-Seok LEE ◽  
Young-Jun LEE ◽  
Dong-Guk HAN ◽  
Ho-Won KIM ◽  
Hyoung-Nam KIM
Keyword(s):  
Performance Improvement ◽  
Power Analysis ◽  
Power Analysis Attacks

Consideration of structural constraints in passive rotor blade design for improved performance

2016 ◽  
Vol 120 (1232) ◽  
pp. 1604-1631 ◽  
Author(s):  
J.W. Lim
Keyword(s):  
Performance Improvement ◽  
Rotor Blade ◽  
Parametric Design ◽  
Control Point ◽  
Bending Moment ◽  
Structural Constraints ◽  
Design Variables ◽  
Significant Performance ◽  
Structural Redesign ◽  
Improved Performance

ABSTRACTThis design study applied parameterisation to rotor blade for improved performance. In the design, parametric equations were used to represent blade planform changes over the existing rotor blade model. Design variables included blade twist, sweep, dihedral and the radial control point. Updates to the blade structural properties with changes in the design variables allowed accurate evaluation of performance objectives and realistic structural constraints – blade stability, steady moments (flap bending, chord bending and torsion) and the high-g manoeuvre pitch link loads. Performance improvement was demonstrated with multiple parametric designs. Using a parametric design with advanced aerofoils, the predicted power reduction was 1.0% in hover, 10.0% at μ = 0.30 and 17.0% at μ = 0.40, relative to the baseline UH-60A rotor, but these were obtained with a 35% increase in the steady chord bending moment at μ = 0.30 and a 20% increase in the half peak-to-peak pitch link load during the UH-60A UTTAS manoeuvre. Low vibration was maintained for this design. More rigorous design efforts, such as chord tapering and/or structural redesign of the blade cross section, would enlarge the feasible design space and likely provide significant performance improvement.

Performance Evaluation of Elliptical-Cylindrical Antenna Array using SaDE Optimized Hyper Beam

2017 ◽  
Vol 7 (1) ◽  
pp. 178 ◽  
Author(s):  
Gebrehiwet Gebrekrstos Lema
Keyword(s):  
Communication Systems ◽  
High Performance ◽  
Optimization Technique ◽  
Analytical Techniques ◽  
Side Lobe ◽  
Optimization Techniques ◽  
Side Lobe Level ◽  
Pattern Synthesis ◽  
Improved Performance ◽  
The Individual

<p>For high performance communication systems, Side Lobe Level (SLL) reduction and improved directivity are the goal of antenna designers. In the recent years, many optimization techniques of antenna design are occupying demanding place over the analytical techniques. Though they have contributed attractive solutions, it is often obvious to select one that meets the particular design need at hand. In this paper, an optimization technique called Self-adaptive Differential Evolution (SaDE) that can be able to learn and behave intelligently along with hyper beam forming is integrated to determine an optimal set of excitation weights in the design of EcAA. Non-uniform excitation weights of the individual array elements of EcAA are performed to obtain reduced SLL, high directivity and flexible radiation pattern. To evaluate the improved performance of the proposed SaDE optimized hyper beam, comparison are done with uniformly excited, SaDE without hyper beam and Genetic Algorithm (GA). In general, the proposed work of pattern synthesis has resulted in much better reduction of SLL and FNBW than both the uniformly excited and thinned EcAA. The results of this study clearly reveal that the SLL highly reduced at a very directive beamwidth.</p>

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