scholarly journals Encoding of Terms in EMB-Based Mealy FSMs

2020 ◽  
Vol 10 (8) ◽  
pp. 2762 ◽  
Author(s):  
Alexander Barkalov ◽  
Larysa Titarenko ◽  
Małgorzata Mazurkiewicz ◽  
Kazimierz Krzywicki
Keyword(s):  
State Transition ◽  
Logic Circuits ◽  
Sequential Algorithm ◽  
State Variables ◽  
Embedded Memory ◽  
Chip Area ◽  
Memory Block ◽  
Finite State ◽  
Transition Table ◽  
Number Of Classes

A method is proposed targeting implementation of FPGA-based Mealy finite state machines. The main goal of the method is a reduction for the number of look-up table (LUT) elements and their levels in FSM logic circuits. To do it, it is necessary to eliminate the direct dependence of input memory functions and FSM output functions on FSM inputs and state variables. The method is based on encoding of the terms corresponding to rows of direct structure tables. In such an approach, only terms depend on FSM inputs and state variables. Other functions depend on variables representing terms. The method belongs to the group of the methods of structural decomposition. The set of terms is divided by classes such that each class corresponds to a single-level LUT-based circuit. An embedded memory block (EMB) generates codes of both classes and terms as elements of these classes. The mutual using LUTs and EMB allows diminishing chip area occupied by FSM circuit (as compared to its LUT-based counterpart). The simple sequential algorithm is proposed for finding the partition of the set of terms by a determined number of classes. The method is based on representation of an FSM by a state transition table. However, it can be used for any known form of FSM specification. The example of synthesis is shown. The efficiency of the proposed method was investigated using a library of standard benchmarks. We compared the proposed with some other known design methods. The investigations show that the proposed method gives better results than other discussed methods. It allows the obtaining of FSM circuits with three levels of logic and regular interconnections.

scholarly journals Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM

2007 ◽  
Vol 17 (4) ◽  
pp. 565-575 ◽  
Author(s):  
Alexander Barkalov ◽  
Larysa Titarenko ◽  
Sławomir Chmielewski
Keyword(s):  
Finite State Machine ◽  
Finite State Machines ◽  
Optimization Methods ◽  
State Machine ◽  
Logic Circuits ◽  
State Machines ◽  
Embedded Memory ◽  
Effective Application ◽  
Finite State

Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSMOptimization methods of logic circuits for Moore finite-state machines are proposed. These methods are based on the existence of pseudoequivalent states of a Moore finite-state machine, a wide fan-in of PAL macrocells and free resources of embedded memory blocks. The methods are oriented to hypothetical VLSI microcircuits based on the CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm to choose the best model of a finite-state machine for given conditions is proposed. Examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated.

Design of EMB-Based Moore FSMs

2017 ◽  
Vol 26 (07) ◽  
pp. 1750125 ◽  
Author(s):  
Małgorzata Kołopieńczyk ◽  
Larysa Titarenko ◽  
Alexander Barkalov
Keyword(s):  
Control Unit ◽  
Logic Circuits ◽  
Embedded Memory ◽  
Complexity Of Algorithms ◽  
Gate Arrays ◽  
Control Units ◽  
Finite State ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Effective Use

The complexity of algorithms implemented in digital systems grows. Methods are developed for most effective use of both hardware resources and energy. For engineers the problem of hardware resources optimization in design of control units is still an important issue. The standard way of implementing the control unit as a finite-state machine (FSM) is not satisfactory as it consumes considerable amounts of field-programmable gate arrays (FPGA) resources. This paper is devoted to the design of a Moore FSM in FPGA structure using look-up tables and embedded memory blocks (EMB) elements. The problem background is discussed. The method of the design of Moore FSM logic circuits with EMB based on splitting the set of logical conditions and the encoding of logical conditions is presented. Examples of design and research results are given.

HYPER-MINIMIZATION FOR DETERMINISTIC TREE AUTOMATA

2013 ◽  
Vol 24 (06) ◽  
pp. 815-830 ◽  
Author(s):  
ARTUR JEŻ ◽  
ANDREAS MALETTI
Keyword(s):  
Finite Difference ◽  
Minimization Problem ◽  
Fast Algorithms ◽  
Input Tree ◽  
Tree Automaton ◽  
Tree Automata ◽  
Compression Technique ◽  
Bottom Up ◽  
Finite State ◽  
Transition Table

Hyper-minimization is a recent automaton compression technique that can reduce the size of an automaton beyond the limits imposed by classical minimization. The additional compression power is enabled by allowing a finite difference in the represented language. The necessary theory for hyper-minimization is developed for (bottom-up) deterministic tree automata. The hyper-minimization problem for deterministic tree automata is reduced to the hyper-minimization problem for deterministic finite-state string automata, for which fast algorithms exist. The fastest algorithm obtained in this way runs in time [Formula: see text], where m is the size of the transition table and n is the number of states of the input tree automaton.

Trustworthy Architecture for Wireless Body Sensor Network

2015 ◽  
pp. 46-80
Author(s):  
G. R. Kanagachidambaresan
Keyword(s):  
Markov Model ◽  
Sensor Network ◽  
Elderly People ◽  
State Transition ◽  
State Machine ◽  
Sensor Nodes ◽  
Monitoring Scheme ◽  
Body Sensor Network ◽  
Finite State ◽  
Physiological Sensors

Wireless Body Sensor Network is a collection of physiological sensors connected to small embedded machines and transceivers to form a monitoring scheme for patients and elderly people. Intrusion and foolproof routing has become mandatory as the Wireless Body Sensor Network has extended its working range. Trust in Wireless Body Sensor Network is greatly determined by the Encryption key size and Energy of the Node. The Sensor Nodes in Wireless Body Sensor Network is powered by small battery banks which are to be removed and recharged often in some cases. Attack to the implanted node in Wireless Body Sensor Network could harm the patient. Finite State Machine helps in realizing the Trust architecture of the Wireless Body Sensor Network. Markov model helps in predicting the state transition from one state to other. This chapter proposes a Trustworthy architecture for creating a trusted and confidential communication for Wireless Body Sensor Network.

USING COMPUTATION TREE LOGIC FOR INTELLIGENT INFORMATION SEARCH ON THE WEB

2002 ◽  
Vol 02 (03) ◽  
pp. 245-253 ◽  
Author(s):  
EUGENIO DI SCIASCIO ◽  
FRANCESCO M. DONINI ◽  
MARINA MONGIELLO
Keyword(s):  
Information Search ◽  
State Transition ◽  
Transition System ◽  
Prototype System ◽  
Retrieval Models ◽  
Computation Tree Logic ◽  
Computation Tree ◽  
Finite State ◽  
State Transition System ◽  
Intelligent Information

Web engines crawl hyperlinks to search for new documents; yet when they index discovered documents they basically revert to conventional information retrieval models and concentrate on the indexing of terms in a single document. We propose to overcome such limits with an approach based on temporal logic. By modeling a web site as a finite state transition system we are able to define complex and selective queries over hyperlinks with the aid of Computation Tree Logic operators. We deployed the proposed approach in a prototype system that allows users pose queries in natural language. Queries are automatically translated in Computation Tree Logic, and the answer returned by our system is a set of paths. Experiments carried out with the aid of human experts show improved retrieval effectiveness with respect to current search engines.

Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs

2019 ◽  
Vol 28 (08) ◽  
pp. 1950131 ◽  
Author(s):  
Alexander Barkalov ◽  
Larysa Titarenko ◽  
Sławomir Chmielewski
Keyword(s):  
Formal Method ◽  
Field Programmable Gate Arrays ◽  
Finite State Machines ◽  
Logic Circuits ◽  
State Machines ◽  
Gate Arrays ◽  
Finite State ◽  
Field Programmable ◽  
Programmable Gate Arrays

A method is proposed targeting the decrease of the number of look-up tables (LUTs) in logic circuits of field programmable gate arrays (FPGA)-based Mealy finite state machines. The method is based on constructing a partition for the set of output variables. It diminishes the number of additional variables encoding the collections of output variables (COVs). A formal method is proposed for finding the partition. An example of synthesis is given, as well as the results of investigations. The investigations were conducted for standard benchmarks.

Statechart-based Controllers Synthesis in FPGA Structures with Embedded Array Blocks

2010 ◽  
Vol 56 (1) ◽  
pp. 13-24 ◽  
Author(s):  
Grzegorz Łabiak ◽  
Grzegorz Borowik
Keyword(s):  
Complex Systems ◽  
Finite State Machine ◽  
Reactive Systems ◽  
State Machine ◽  
Embedded Memory ◽  
Digital Controllers ◽  
Functional Decomposition ◽  
Finite State ◽  
Implementation Scheme ◽  
Programmable Devices

Statechart-based Controllers Synthesis in FPGA Structures with Embedded Array BlocksStatechart diagrams, in general, are visual formalism for description of complex systems behaiour. Digital controllers, which act as reactive systems, can be very conveniently modeled with statecharts and efficiently synthesized in modern programmable devices. The paper presents in details syntax and semantics of statecharts and new implementation scheme. The issue of statecharts synthesis is not still ultimately solved. Main feature of the presented approach is the transformation of statechart diagrams into Finite State Machine, and through KISS format, functional decomposition and mapping into Embedded Memory Blocks. Embedded Memory are part of the modern programmable devices.

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