scholarly journals Atomic Layer Deposition of High-k Insulators on Epitaxial Graphene: A Review

2020 ◽  
Vol 10 (7) ◽  
pp. 2440 ◽  
Author(s):  
Filippo Giannazzo ◽  
Emanuela Schilirò ◽  
Raffaella Lo Nigro ◽  
Fabrizio Roccaforte ◽  
Rositsa Yakimova
Keyword(s):  
Atomic Layer Deposition ◽  
Critical Role ◽  
Atomic Layer ◽  
Epitaxial Graphene ◽  
Organic Monolayers ◽  
Layer Deposition ◽  
High K ◽  
Deposited Metal ◽  
High K Materials ◽  
The Impact

Due to its excellent physical properties and availability directly on a semiconductor substrate, epitaxial graphene (EG) grown on the (0001) face of hexagonal silicon carbide is a material of choice for advanced applications in electronics, metrology and sensing. The deposition of ultrathin high-k insulators on its surface is a key requirement for the fabrication of EG-based devices, and, in this context, atomic layer deposition (ALD) is the most suitable candidate to achieve uniform coating with nanometric thickness control. This paper presents an overview of the research on ALD of high-k insulators on EG, with a special emphasis on the role played by the peculiar electrical/structural properties of the EG/SiC (0001) interface in the nucleation step of the ALD process. The direct deposition of Al2O3 thin films on the pristine EG surface will be first discussed, demonstrating the critical role of monolayer EG uniformity to achieve a homogeneous Al2O3 coverage. Furthermore, the ALD of several high-k materials on EG coated with different seeding layers (oxidized metal films, directly deposited metal-oxides and self-assembled organic monolayers) or subjected to various prefunctionalization treatments (e.g., ozone or fluorine treatments) will be presented. The impact of the pretreatments and of thermal ALD growth on the defectivity and electrical properties (doping and carrier mobility) of the underlying EG will be discussed.

Seeding Atomic Layer Deposition of High-k Dielectrics on Epitaxial Graphene with Organic Self-Assembled Monolayers

ACS Nano ◽  
2011 ◽  
Vol 5 (6) ◽  
pp. 5223-5232 ◽  
Author(s):  
Justice M. P. Alaboson ◽  
Qing Hua Wang ◽  
Jonathan D. Emery ◽  
Albert L. Lipson ◽  
Michael J. Bedzyk ◽  
...  
Keyword(s):  
Atomic Layer Deposition ◽  
Atomic Layer ◽  
Epitaxial Graphene ◽  
Self Assembled Monolayers ◽  
Layer Deposition ◽  
High K ◽  
Assembled Monolayers ◽  
Self Assembled

Atomic Layer Deposition of Zirconium-Based High-k Metal Gate Oxide: Effect of Si Containing Zr Precursor

2015 ◽  
Vol 15 (1) ◽  
pp. 382-385
Author(s):  
Jun Hee Cho ◽  
Sang-Ick Lee ◽  
Jong Hyun Kim ◽  
Sang Jun Yim ◽  
Hyung Soo Shin ◽  
...  
Keyword(s):  
Atomic Layer Deposition ◽  
Atomic Layer ◽  
Gate Oxide ◽  
Metal Gate ◽  
Layer Deposition ◽  
High K

Design, Simulation and Testing of High Density, High Current Micro-machined Embedded Capacitors

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000515-000534
Author(s):  
Aubrey Beal ◽  
C. Stevens ◽  
T. Baginski ◽  
M. Hamilton ◽  
R. Dean
Keyword(s):  
Integrated Circuits ◽  
Hafnium Oxide ◽  
Implementation Strategies ◽  
Atomic Layer ◽  
High Density ◽  
Embedded Capacitors ◽  
Passive Devices ◽  
Layer Deposition ◽  
High K ◽  
High K Materials

Due to increasing speed, density and number of signal paths in integrated circuits, motivations for high density capacitors capable of quickly sourcing large amounts of current have led to many design and fabrication investigations. This work outlines continued efforts to achieve devices which meet these stringent requirements and are compatible with standard silicon fabrication processes as well as silicon interposer technologies. Previous work has been further developed resulting in devices exhibiting greater capacitance values by employing geometries which maximize surface area. The Atomic Layer Deposition (ALD) of thin layered high K materials, such as Hafnium Oxide, as opposed to previous silicon-dioxide based devices effectively increased the capacitance per unit area of the structures. This paper outlines the design, fabrication, and testing of high density micro-machined embedded capacitors capable of quickly sourcing (i.e. risetimes greater than 100A/nsec) high currents (i.e. greater than 100A). These devices were successfully simulated then tested using a standard ringdown procedure. Generally, the resulting device characterization found during testing stages strongly correlates to the expected simulated device behavior. Subsequent descriptions and design challenges encountered during fabrication, testing and integration of these passive devices are outlined, as well as potential device integration and implementation strategies for use in silicon interposers. The modification and revision of several device generations is documented and presented. Increased device capacitive density, maximized current capabilities and minimized effects of series inductance and resistance are presented. These resulting thin, capacitive structures exhibit compatibility with Si interposer technology.

scholarly journals Conformal High-K Dielectric Coating of Suspended Single-Walled Carbon Nanotubes by Atomic Layer Deposition

Nanomaterials ◽  
2019 ◽  
Vol 9 (8) ◽  
pp. 1085 ◽  
Author(s):  
Kemelbay ◽  
Tikhonov ◽  
Aloni ◽  
Kuykendall
Keyword(s):  
Carbon Nanotubes ◽  
Atomic Layer Deposition ◽  
Field Effect Transistors ◽  
Atomic Layer ◽  
Oxide Thickness ◽  
Ambient Conditions ◽  
Nucleation Layer ◽  
Layer Deposition ◽  
High K ◽  
High K Dielectric

As one of the highest mobility semiconductor materials, carbon nanotubes (CNTs) have been extensively studied for use in field effect transistors (FETs). To fabricate surround-gate FETs— which offer the best switching performance—deposition of conformal, weakly-interacting dielectric layers is necessary. This is challenging due to the chemically inert surface of CNTs and a lack of nucleation sites—especially for defect-free CNTs. As a result, a technique that enables integration of uniform high-k dielectrics, while preserving the CNT’s exceptional properties is required. In this work, we show a method that enables conformal atomic layer deposition (ALD) of high-k dielectrics on defect-free CNTs. By depositing a thin Ti metal film, followed by oxidation to TiO2 under ambient conditions, a nucleation layer is formed for subsequent ALD deposition of Al2O3. The technique is easy to implement and is VLSI-compatible. We show that the ALD coatings are uniform, continuous and conformal, and Raman spectroscopy reveals that the technique does not induce defects in the CNT. The resulting bilayer TiO2/Al2O3 thin-film shows an improved dielectric constant of 21.7 and an equivalent oxide thickness of 2.7 nm. The electrical properties of back-gated and top-gated devices fabricated using this method are presented.

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