scholarly journals Failure Analysis of SAC305 Ball Grid Array Solder Joint at Extremely Cryogenic Temperature

2020 ◽  
Vol 10 (6) ◽  
pp. 1951 ◽  
Author(s):  
Yanruoyue Li ◽  
Guicui Fu ◽  
Bo Wan ◽  
Maogong Jiang ◽  
Weifang Zhang ◽  
...  
Keyword(s):  
Low Temperature ◽  
Solder Joint ◽  
Failure Analysis ◽  
Sem Analysis ◽  
Circuit Board ◽  
Space Environment ◽  
Fracture Characteristic ◽  
Characteristic Change ◽  
Shock Test ◽  
Cause Of Failure

To verify the reliability of a typical Pb-free circuit board applied for space exploration, five circuits were put into low temperature and shock test. However, after the test, memories on all five circuits were out of function. To investigate the cause of the failure, a series of methods for failure analysis was carried out, including X-ray detection, cross-section analysis, Scanning Electron Microscope (SEM) analysis, and contrast test. Through failure analysis, the failure was located in the Pb-free (Sn-3.0Ag-0.5Cu) solder joint, and we confirmed that the failure occurred because of the low temperature and change of fracture characteristic of Sn-3.0Ag-0.5Cu (SAC305). A verification test was conducted to verify the failure mechanism. Through analyzing data and fracture surface morphology, the cause of failure was ascertained. At low temperature, the fracture characteristic of SAC305 changed from ductileness to brittleness. The crack occurred at solder joints because of stress loaded by shock test. When the crack reached a specific length, the failure occurred. The temperature of the material’s characteristic change was −70–−80 °C. It could be a reference for Pb-free circuit board use in a space environment.

Reliability Failure Analysis of PCB and its Technological Improvement

2013 ◽  
Vol 401-403 ◽  
pp. 391-394 ◽  
Author(s):  
Li Fang Zhu
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Board ◽  
Test Method ◽  
Circuit Board ◽  
Design And Technology ◽  
Thermal Shock Test ◽  
Shock Test ◽  
Technological Improvement ◽  
Electrical Interconnection ◽  
Improved Technology

Reliability failure analysis is extremely important in the manufacturing process of PCB (Printed Circuit Board). In this paper, we use thermal shock test method to analysis the electrical interconnection reliability of PCB in harsh environment. Also taking into account the reliability of PCB is closely related to its design and technology, approaches of technological improvement are proposed. Finally through temperature shock test method, the results show that the reliability of PCB designed with improved technology is enhanced.

Creep-caused fracture of PbSn solder joint

2017 ◽  
Vol 31 (16-19) ◽  
pp. 1744008
Author(s):  
M. Meng ◽  
Z. B. Wang ◽  
X. Wang ◽  
Y. Chen
Keyword(s):  
Solder Joint ◽  
Failure Analysis ◽  
Stress Level ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Fracture Morphology ◽  
Circuit Board ◽  
Electronic Assembly ◽  
Printed Circuit ◽  
Pbsn Solder

This paper analyzes two failure cases of creep-caused fracture of PbSn solder joint, including the joint between the wire and solder cup in the connector and the joint between the integrated circuit (IC) pins and the printed circuit board (PCB). The environment conditions, for the creep of PbSn solder joint is demonstrated, including the temperature and stress level. The stress origin and fracture morphology are summarized based on the failure analysis. Besides, the developing process of creep-caused fracture is explained. The paper comprehensively clarifies the creep mechanism of PbSn solder and consequently provides significant guidance for the reliable electronic assembly to avoid the creep-caused damage.

Development of High Permeability Core Materials for Embeddable Inductors in Flexible Organic Substrates

2003 ◽  
Vol 769 ◽  
Author(s):  
C. K. Liu ◽  
P. L. Cheng ◽  
S. Y. Y. Leung ◽  
T. W. Law ◽  
D. C. C. Lam
Keyword(s):  
Low Temperature ◽  
Sol Gel ◽  
Circuit Board ◽  
Organic Substrates ◽  
Circuit Boards ◽  
High Permeability ◽  
Electrical Measurements ◽  
Different Temperatures ◽  
Spiral Inductors ◽  
Ceramic Tape

AbstractCapacitors, resistors and inductors are surface mounted components on circuit boards, which occupy up to 70% of the circuit board area. For selected applications, these passives are packaged inside green ceramic tape substrates and sintered at temperatures over 700°C in a co-fired process. These high temperature processes are incompatible with organic substrates, and low temperature processes are needed if passives are to be embedded into organic substrates. A new high permeability dual-phase Nickel Zinc Ferrite (DP NZF) core fabricated using a low temperature sol-gel route was developed for use in embedded inductors in organic substrates. Crystalline NZF powder was added to the sol-gel precursor of NZF. The solution was deposited onto the substrates as thin films and heat-treated at different temperatures. The changes in the microstructures were characterized using XRD and SEM. Results showed that addition of NZF powder induced low temperature transformation of the sol-gel NZF phase to high permeability phase at 250°C, which is approximately 350°C lower than transformation temperature for pure NZF sol gel films. Electrical measurements of DP NZF cored two-layered spiral inductors indicated that the inductance increased by three times compared to inductors without the DP NZF cores. From microstructural observations, the increase is correlated with the changes in microstructural connectivity of the powder phase.

Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint

2004 ◽  
Author(s):  
Norman J. Armendariz ◽  
Prawin Paulraj
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Gold Surface ◽  
Circuit Board ◽  
Lead Free ◽  
Processing Temperature ◽  
The European Union ◽  
Printed Circuit ◽  
Higher Temperature ◽  
Tin Silver Copper

Abstract The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.

Reballing/Rebumping Ultra-Fine Pitch Packages Less Than 0.5 mm Pitch for FA

2014 ◽  
Author(s):  
Bob Wettermann
Keyword(s):  
Solder Joint ◽  
Failure Analysis ◽  
Joint Strength ◽  
Semiconductor Devices ◽  
X Ray ◽  
Fine Pitch ◽  
Manual Methods

Abstract As the pitch and package sizes of semiconductor devices have shrunk and their complexity has increased, the manual methods by which the packages can be re-bumped or reballed for failure analysis have not kept up with this miniaturization. There are some changes in the types of reballing preforms used in these manual methods along with solder excavation techniques required for packages with pitches as fine as 0.3mm. This paper will describe the shortcomings of the previous methods, explain the newer methods and materials and demonstrate their robustness through yield, mechanical solder joint strength and x-ray analysis.

Case Study—Failure Analysis of a Multiplexer

2016 ◽  
Author(s):  
Michael Woo ◽  
Marcos Campos ◽  
Luigi Aranda
Keyword(s):  
Failure Analysis ◽  
High Reliability ◽  
Component Failure ◽  
Root Cause ◽  
Knowing That ◽  
Cause Of Failure ◽  
The Cost

Abstract A component failure has the potential to significantly impact the cost, manufacturing schedule, and/or the perceived reliability of a system, especially if the root cause of the failure is not known. A failure analysis is often key to mitigating the effects of a componentlevel failure to a customer or a system; minimizing schedule slips, minimizing related accrued costs to the customer, and allowing for the completion of the system with confidence that the reliability of the product had not been compromised. This case study will show how a detailed and systemic failure analysis was able to determine the exact cause of failure of a multiplexer in a high-reliability system, which allowed the manufacturer to confidently proceed with production knowing that the failure was not a systemic issue, but rather that it was a random “one time” event.

Infra-Red Reflectance Microscopy (IRRM) for Daisy Chain Flip Chip Device Failure Analysis

2004 ◽  
Author(s):  
Carlo Grilletto ◽  
Steve Hsiung ◽  
Andrew Komrowski ◽  
John Soopikian ◽  
Daniel J.D. Sullivan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
State Of The Art ◽  
Failure Mechanisms ◽  
Simple Metal ◽  
X Ray ◽  
Infra Red ◽  
Cause Of Failure ◽  
Reflectance Microscopy ◽  
Ir Emission

Abstract This paper describes a method to "non-destructively" inspect the bump side of an assembled flip-chip test die. The method is used in conjunction with a simple metal-connecting "modified daisy chain" die and makes use of the fact that polished silicon is transparent to infra-red (IR) light. The paper describes the technique, scope of detection and examples of failure mechanisms successfully identified. It includes an example of a shorting anomaly that was not detectable with the state of the art X-ray equipment, but was detected by an IR emission microscope. The anomalies, in many cases, have shown to be the cause of failure. Once this has been accomplished, then a reasonable deprocessing plan can be instituted to proceed with the failure analysis.

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