scholarly journals Hardware Implementation of Chaotic Zigzag Map Based Bitwise Dynamical Pseudo Random Number Generator on Field-Programmable Gate Array

2021 ◽  
Vol 11 (8) ◽  
pp. 3330
Author(s):  
Pietro Nannipieri ◽  
Stefano Di Matteo ◽  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Jacopo Belli ◽  
...  

Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.


Author(s):  
Mohamed Saber ◽  
Marwa M. Eid

Lemniscate chaotic map (LCM) provides a wide range of control parameters, canceling the need for several rounds of substitutions, and excellent performance in the confusion process. Unfortunately, the hardware model of LCM is complex and consumes high power. This paper presents a proposed low power hardware model of LCM called practical lemniscate chaotic map (P-LCM) depending on trigonometric identities to reduce the complexity of the conventional model. The hardware model designed and implement into the field programmable gate array (FPGA) board, Spartan-6 SLX45FGG484-3. The proposed model achieves a 48.3 % reduction in used resources and a 34.6 % reduction in power consumption compared to the conventional LCM. We also introduce a new pseudo-random number generator based on a proposed low power P-LCM model and perform the randomization tests for the proposed encryption system.


2013 ◽  
Vol 16 (2) ◽  
pp. 210-216 ◽  
Author(s):  
Sattar B. Sadkhan ◽  
◽  
Sawsan K. Thamer ◽  
Najwan A. Hassan ◽  
◽  
...  

Micromachines ◽  
2020 ◽  
Vol 12 (1) ◽  
pp. 31
Author(s):  
Junxiu Liu ◽  
Zhewei Liang ◽  
Yuling Luo ◽  
Lvchen Cao ◽  
Shunsheng Zhang ◽  
...  

Recent research showed that the chaotic maps are considered as alternative methods for generating pseudo-random numbers, and various approaches have been proposed for the corresponding hardware implementations. In this work, an efficient hardware pseudo-random number generator (PRNG) is proposed, where the one-dimensional logistic map is optimised by using the perturbation operation which effectively reduces the degradation of digital chaos. By employing stochastic computing, a hardware PRNG is designed with relatively low hardware utilisation. The proposed hardware PRNG is implemented by using a Field Programmable Gate Array device. Results show that the chaotic map achieves good security performance by using the perturbation operations and the generated pseudo-random numbers pass the TestU01 test and the NIST SP 800-22 test. Most importantly, it also saves 89% of hardware resources compared to conventional approaches.


Electronics ◽  
2020 ◽  
Vol 10 (1) ◽  
pp. 16
Author(s):  
Sehoon Lee ◽  
Myungseo Park ◽  
Jongsung Kim

With the rapid increase in computer storage capabilities, user data has become increasingly important. Although user data can be maintained by various protection techniques, its safety has been threatened by the advent of ransomware, defined as malware that encrypts user data, such as documents, photographs and videos, and demands money to victims in exchange for data recovery. Ransomware-infected files can be recovered only by obtaining the encryption key used to encrypt the files. However, the encryption key is derived using a Pseudo Random Number Generator (PRNG) and is recoverable only by the attacker. For this reason, the encryption keys of malware are known to be difficult to obtain. In this paper, we analyzed Magniber v2, which has exerted a large impact in the Asian region. We revealed the operation process of Magniber v2 including PRNG and file encryption algorithms. In our analysis, we found a vulnerability in the PRNG of Magniber v2 developed by the attacker. We exploited this vulnerability to successfully recover the encryption keys, which was by verified the result in padding verification and statistical randomness tests. To our knowledge, we report the first recovery result of Magniber v2-infected files.


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