scholarly journals High gain and Low power Up conversion Mixer for Wireless LAN Applications

2019 ◽  
pp. 179-185
Author(s):  
Ananda M ◽  
A B Kalpana
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Wireless Lan ◽  
Intermediate Frequency ◽  
Local Oscillator ◽  
High Gain ◽  
Conversion Gain ◽  
Third Order ◽  
Voltage Conversion ◽  
Intercept Point

This work aims an efficient RF Up-Conversion Mixer at Intermediate frequency of 100MHz and Local oscillator frequency of 2.3GHz. The proposed RF Up-Conversion Mixer exhibited better performance in terms of parameter like conversion gain and power consumption. The Simulation of Up-Conversion Mixer shows that the results of voltage conversion gain with LO power at 0dB is 5dB, at 5dB is 4.9dB, and at 10dB is 4.7dB. The power consumption of proposed design is 6mW. The 1dB compression point is -5.43dBm and third order intercept point is 10.53dBm.

scholarly journals A Wideband Subharmonic Mixer Incorporating Signal Interference Technique Based Isolation Circuit

2019 ◽  
Vol 9 (2) ◽  
pp. 132-136
Keyword(s):  
Intermediate Frequency ◽  
Local Oscillator ◽  
Signal Interference ◽  
Frequency Range ◽  
Conversion Loss ◽  
Large Signal ◽  
Third Order ◽  
Single Sideband ◽  
Down Conversion ◽  
Intercept Point

A broadband (8.7 GHz – 11.5 GHz) performing passive sub-harmonic down-conversion mixer using signal interference technique (SIT) is demonstrated, designed and reported in this paper. The local oscillator (LO) frequency is half of the radio frequency (RF) for the 2xsub-harmonic mixer architecture; therefore, for the RF lying in the range 8.7 GHz to 11.5 GHz, required LO frequency range is 4.25 GHz to 5.65 GHz with 0.2 GHz fixed intermediate frequency (IF). With a broadband operation, designed prototype shows single sideband down-conversion loss in the range 9.6 dB – 12.6 dB. Moreover, large-signal testing infers an adequate linear trait of the proposed design, showing -3 dBm and 11.32 dBm for the 1 dB compression point and third order input intercept point, respectively.

A Low Power CMOS Bulk-Controlled Sub-Harmonic Mixer for LTE-Advanced Applications

2013 ◽  
Vol 284-287 ◽  
pp. 2423-2427
Author(s):  
Hung Che Wei ◽  
Chih Lung Hsiao
Keyword(s):  
Low Power ◽  
Power Conversion ◽  
Local Oscillator ◽  
Rf Cmos ◽  
Third Order ◽  
Harmonic Mixer ◽  
Lte Advanced ◽  
Low Power Cmos ◽  
Intercept Point ◽  
Advanced Applications

In this paper, a 3.5 GHz CMOS sub-harmonic mixer for LTE-advanced applications is presented. The mixer with the bulk-controlled technique improves the linearity and mitigates the power of the local oscillator. The proposed mixer is implemented by tsmc 0.18 μm Mixed Signal RF CMOS 1P6M process and consumes 2.2 mA from a 1.2 V supply. The proposed mixer operates at 3.5GHz LTE-advanced bands and achieves maximum input third-order intercept point (IIP3) of 2.3dBm, power conversion gains of 1.3 dB.

Low Voltage Low Power Folded Mixer for S-Band Wireless Applications

Frequenz ◽  
2014 ◽  
Vol 68 (11-12) ◽  
Author(s):  
Shiqiang Chen ◽  
Junfeng Wang
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Intermediate Frequency ◽  
Local Oscillator ◽  
Conversion Gain ◽  
Chip Area ◽  
Wireless Applications ◽  
Dc Power ◽  
Rf Signal

AbstractThis paper describes a low voltage low power (LV-LP) folded mixer for S-band wireless applications. The proposed mixer could convert a 10 MHz intermediate frequency (IF) signal to a 2.4 GHz RF signal with a local oscillator (LO) power of 0 dBm at 2.39 GHz. The comparison with the previous reported mixers shows that the proposed mixer has the advantages of lower voltage, lower power consumption and higher conversion gain than most of the other works. Simulation results demonstrate that the mixer a remarkable conversion gain of 10.5 dB while consuming only 0.65 mW DC power from a 0.8 V supply voltage. The input-referred third-order intercept point (IIP3) of the mixer is 3.75 dBm, and the chip area is only 0.525 mm

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

Flexible low-power source-gated transistors with solution-processed metal–oxide semiconductors

Nanoscale ◽  
2020 ◽  
Vol 12 (42) ◽  
pp. 21610-21616
Author(s):  
Dingwei Li ◽  
Momo Zhao ◽  
Kun Liang ◽  
Huihui Ren ◽  
Quantan Wu ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Power Consumption ◽  
Low Power ◽  
High Gain ◽  
Power Source ◽  
Metal Oxide Semiconductors ◽  
Low Power Consumption ◽  
Light Weight ◽  
Solution Processed ◽  
Oxide Semiconductors

Flexible light weight In2O3-based source-gated transistors are achieved with high gain, fast saturation and low power consumption.

A GaAs monolithic amplifier with extremely low power consumption

1991 ◽  
Vol 69 (3-4) ◽  
pp. 177-179
Author(s):  
Langis Roy ◽  
Malcolm G. Stubbs ◽  
James S. Wight
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Gain ◽  
Low Power Consumption ◽  
Monolithic Microwave Integrated Circuit ◽  
Dc Power ◽  
Broadband Amplifier ◽  
Effect Transistor ◽  
And Performance

The design and performance of a high-gain, monolithic, broadband amplifier with extremely low power consumption are described. The amplifier, fabricated using a 0.5 μm GaAs depletion-mode MESFET (metal semiconductor field effect transistor) process, utilizes very small gate width devices to achieve a measured gain of 19 dB and a 0.1 to 2.1 GHz bandwidth with only 63 mW dc power dissipation. This is the lowest power consumption broadband MMIC (monolithic microwave integrated circuit) reported to date and is intended for mobile radio applications.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

scholarly journals 50 MHz–10 GHz Low-Power Resistive Feedback Current-Reuse Mixer with Inductive Peaking for Cognitive Radio Receiver

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Nandini Vitee ◽  
Harikrishnan Ramiah ◽  
Wei-Keat Chong ◽  
Gim-Heng Tan ◽  
Jeevan Kanesan ◽  
...  
Keyword(s):  
Cognitive Radio ◽  
Power Consumption ◽  
Low Power ◽  
Noise Figure ◽  
Cmos Technology ◽  
Radio Receiver ◽  
Conversion Gain ◽  
Current Reuse ◽  
Inductive Peaking ◽  
Resistive Feedback

A low-power wideband mixer is designed and implemented in 0.13 µm standard CMOS technology based on resistive feedback current-reuse (RFCR) configuration for the application of cognitive radio receiver. The proposed RFCR architecture incorporates an inductive peaking technique to compensate for gain roll-off at high frequency while enhancing the bandwidth. A complementary current-reuse technique is used between transconductance and IF stages to boost the conversion gain without additional power consumption by reusing the DC bias current of the LO stage. This downconversion double-balanced mixer exhibits a high and flat conversion gain (CG) of 14.9 ± 1.4 dB and a noise figure (NF) better than 12.8 dB. The maximum input 1-dB compression point (P1dB) and maximum input third-order intercept point (IIP3) are −13.6 dBm and −4.5 dBm, respectively, over the desired frequency ranging from 50 MHz to 10 GHz. The proposed circuit operates down to a supply headroom of 1 V with a low-power consumption of 3.5 mW.

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