Low Power Design for CMOS Circuits

P. Kalyani;

doi:10.32377/cvrjst0306

Low Power Design for CMOS Circuits

CVR Journal of Science & Technology ◽

10.32377/cvrjst0306 ◽

2012 ◽

Vol 03 (1) ◽

pp. 29-31

Author(s):

P. Kalyani ◽

Keyword(s):

Low Power ◽

Low Power Design ◽

Cmos Circuits

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Low-power design of high-capacitive CMOS circuits using a new charge sharing scheme

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278) ◽

10.1109/isscc.1999.759257 ◽

2003 ◽

Cited By ~ 8

Author(s):

M.M. Khellah ◽

M.I. Elmasry

Keyword(s):

Low Power ◽

Low Power Design ◽

Cmos Circuits ◽

Charge Sharing ◽

Sharing Scheme

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Efficiency of low-power design techniques in multi-gate FET CMOS circuits

ESSDERC 2007 - 37th European Solid State Device Research Conference ◽

10.1109/essderc.2007.4430891 ◽

2007 ◽

Cited By ~ 2

Author(s):

C. Pacha ◽

K. von Arnim ◽

F. Bauer ◽

T. Schulz ◽

W. Xiong ◽

...

Keyword(s):

Low Power ◽

Low Power Design ◽

Cmos Circuits ◽

Design Techniques

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Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '11 ◽

10.1145/1973009.1973062 ◽

2011 ◽

Author(s):

Sudarshan Srinivasan ◽

Bharath Phanibhushana ◽

Arunkumar Vijayakumar ◽

Sandip Kundu

Keyword(s):

Low Power ◽

Low Power Design ◽

Cmos Circuits ◽

Switching Activity ◽

Nanoscale Cmos ◽

Critical Paths

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Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference ◽

10.1109/esscirc.2007.4430258 ◽

2007 ◽

Author(s):

C. Pacha ◽

K. von Arnim ◽

F. Bauer ◽

T. Schulz ◽

W. Xiong ◽

...

Keyword(s):

Low Power ◽

Low Power Design ◽

Cmos Circuits ◽

Design Techniques

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Power mad [low-power design]

Power Engineering Journal ◽

10.1049/pe:20040307 ◽

2004 ◽

Vol 18 (3) ◽

pp. 37

Author(s):

J. Frenkil

Keyword(s):

Low Power ◽

Low Power Design

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LOW POWER DESIGN FOR TESTABILITY IMPLEMENTATION FOR ASYNCHRONOUS FIFO

i-manager’s Journal on Electronics Engineering ◽

10.26634/jele.9.2.15142 ◽

2019 ◽

Vol 9 (2) ◽

pp. 24

Author(s):

KUMAR PATNALA MADHU ◽

R. NAGENDRA ◽

◽

Keyword(s):

Low Power ◽

Low Power Design ◽

Design For Testability

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An Ultra-Low-Power Design of Smart Wearable Stereo Camera

SoutheastCon 2021 ◽

10.1109/southeastcon45413.2021.9401833 ◽

2021 ◽

Author(s):

Ernesto Sola-Thomas ◽

Masudul Haider Imtiaz

Keyword(s):

Low Power ◽

Low Power Design ◽

Ultra Low Power ◽

Stereo Camera ◽

Smart Wearable

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Low power design challenges for the decade (invited talk)

Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01 ◽

10.1145/370155.370356 ◽

2001 ◽

Cited By ~ 17

Author(s):

Shekhar Borkar

Keyword(s):

Low Power ◽

Low Power Design ◽

Design Challenges

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Is Your Low Power Design Switched On?

2007 International Symposium on System-on-Chip ◽

10.1109/issoc.2007.4427451 ◽

2007 ◽

Cited By ~ 2

Author(s):

Mark Croft ◽

Stephen Bailey

Keyword(s):

Low Power ◽

Low Power Design

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Low Power Design from Technology Challenge to Great Products

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.2006.4271838 ◽

2006 ◽

Cited By ~ 1

Author(s):

Barry Dennington

Keyword(s):

Low Power ◽

Low Power Design

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