scholarly journals Assertion Driven Modified Booth Encoding and Post Computation Model for Speed MAC Applications

2021 ◽  
Author(s):  
S. Sivasaravanababu ◽  
T.R. Dineshkumar ◽  
G. Saravana Kumar
Keyword(s):  
Computational Complexity ◽  
High Speed ◽  
High Performance ◽  
Complexity Reduction ◽  
Partial Product ◽  
Path Delay ◽  
Overall Design ◽  
Look Ahead ◽  
Wireless Application ◽  
Product Accumulation

The Multiply-Accumulate Unit (MAC) is the core computational block in many DSP and wireless application but comes with more complicated architectures. Moreover the MAC block also decides the energy consumption and the performance of the overall design; due to its lies in the maximal path delay critical propagation. Developing high performance and energy optimized MAC core is essential to optimized DSP core. In this work, a high speed and low power signed booth radix enabled MAC Unit is proposed with highly configurable assertion driven modified booth algorithm (AD-MBE). The proposed booth core is based on core optimized booth radix-4 with hierarchical partial product accumulation design and associated path delay optimization and computational complexity reduction. Here all booth generated partial products are added as post summation adder network which consists of carry select adder (CSA) & carry look ahead (CLA) sequentially which narrow down the energy and computational complexity. Here increasing the operating frequency is achieved by accumulating encoding bits of each of the input operand into assertion unit before generating end results instead of going through the entire partial product accumulation. The FPGA implementation of the proposed signed asserted booth radix-4 based MAC shows significant complexity reduction with improved system performance as compared to the conventional booth unit and conventional array multiplier.

A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics

2019 ◽  
Vol 15 (3) ◽  
pp. 302-308
Author(s):  
Ganesh Kumar Ganjikunta ◽  
Sibghatullah I. Khan ◽  
M. Mahaboob Basha
Keyword(s):  
High Speed ◽  
High Performance ◽  
Partial Product ◽  
Vedic Mathematics ◽  
Regular Shape ◽  
Power Delay Product ◽  
Product Output ◽  
Multiplier Circuit

A high speed N × N bit multiplier architecture that supports signed and unsigned multiplication operations is proposed in this paper. This architecture incorporates the modified two's complement circuits and also N × N bit unsigned multiplier circuit. This unsigned multiplier circuit is based on decomposing the multiplier circuit into smaller-precision independent multipliers using Vedic Mathematics. These individual multipliers generate the partial products in parallel for high speed operation, which are combined by using high speed adders and parallel adder to generate the product output. The proposed architecture has regular-shape for the partial product tree that makes easy to implement. Finally, this multiplier architecture is implemented in UMC 65 nm technology for N = 8, 16 and 32 bits. The synthesis results shows that the proposed multiplier architecture improves in terms of speed and also reduces power-delay product (PDP), compared to the architectures in the literature.

scholarly journals VLSI Architecture of High Performance Multiplier for High Speed Applications

2020 ◽  
Vol 9 (3) ◽  
pp. 442-445
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Vlsi Architecture ◽  
Digital Signal ◽  
Full Adder ◽  
Vital Role ◽  
Path Delay

In the application of digital signal process multipliers play a vital role. With advances in technology, several researchers have tried and try to design multipliers which supply high speed, low power consumption, regularity of layout and thus less space or maybe combination of them in one multiplier factor. Thus, Compact VLSI design for four bit multiplier factor is planned during this paper that is appropriate for low power and high speed applications. Multiplier factor with high performance is achieved through the novel style of hybrid single bit full adder and Dadda algorithmic rule. The important path delay and power consumption of the planned multiplier factor square measure reduced by 65.9% and 24.5% severally when put next with existing multipliers. The planned multiplier factor is synthesized exploitation CADENCE five.1.0 EDA tool and simulated exploitation spectre virtuoso.

scholarly journals Design of High Performance Modified Wave pipelined DAA Filter with Critical Path Approach

2012 ◽  
pp. 78-82
Author(s):  
Charanjit Singh ◽  
Balwinder Singh
Keyword(s):  
High Speed ◽  
High Performance ◽  
Critical Path ◽  
Fir Filter ◽  
Control Circuit ◽  
Path Delay ◽  
Clock Skew ◽  
Wide Range ◽  
Wave Pipelining ◽  
The Cost

In this paper, a new high speed control circuit is proposed which will act as a critical path for the data which will go from input to output to improve the performance of wave pipelining circuits The wave pipelining is a method of high performance circuit designs which implements pipelining in logic without the use of intermediate registers. Wave pipelining has been widely used in the past few years with a great deal of significant features in technology and applications. It has the ability to improve speed, efficiency, economy in every aspect which it presents. Wave pipelining is being used in wide range of applications like digital filters, network routers, multipliers, fast convolvers, MODEMs, image processing, control systems, radars and many others. In previous work, the operating speed of the wave-pipelined circuit can be increased by the following three tasks: adjustment of the clock period, clock skew and equalization of path delays. The path-delay equalization task can be done theoretically, but the real challenge is to accomplish it in the presence of various different delays. So, the main objective of this paper is to solve the path delay equalization problem by inserting the control circuit in wave pipelined based circuit which will act as critical path for the data that moves from input to output. The proposed technique is evaluated for DSP applications by designing 4- tap FIR filter using Distributed arithmetic algorithm (DAA). Then comparison of this design is done with 4-tap FIR filter designs using conventional pipelining and non pipelining. The synthesis and simulation results based on Xilinx ISE Navigator 12.3 shows that wave pipelined DAA based filter is faster by a factor of 1.43 compared to non pipelined one and the conventional pipelined filter is faster than non pipelined by factor of 1.61 but at the cost of increased logic utilization by 200 %. So, the wave-pipelined DA filters designed with the proposed control circuit can operate at higher frequency than that of non-pipelined but less than that of pipelined. The gain in speed in pipelined compared to that of wavepipelined is at the cost of increased area and more dissipated power. When latency is considered, wavepipelined design filters with the proposed scheme are having the lowest latency among three schemes designed.

scholarly journals VLSI Implementation of Reconfigurable FFT Processor Using Vedic Mathematics

2015 ◽  
Vol 5 (2) ◽  
Author(s):  
Bharatha K. Babu ◽  
G. Nanthini
Keyword(s):  
Fourier Transform ◽  
Small Area ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Path Delay ◽  
Vedic Mathematics ◽  
Fft Processor ◽  
Wide Range ◽  
Single Path

Fast Fourier transform has been used in wide range of applications such as digital signal processing and wireless communications. In this we present a implementation of reconfigurable FFT processor using single path delay feedback architecture. To eliminate the use of read only memory’s (ROM’S). These are used to store the twiddle factors. To achieve the ROM-less FFT processor the proposed architecture applies the bit parallel multipliers and reconfigurable complex multipliers, thus consuming less power. The proposed architecture, Reconfigurable FFT processor based on Vedic mathematics is designed, simulated and implemented using VIRTEX-5 FPGA. Urdhva Triyakbhyam algorithm is an ancient Vedic mathematic sutra, which is used to achieve the high performance. This reconfigurable DIF-FFT is having the high speed and small area as compared with other conventional DIF-FFT

Vacuum System to Minimize the Specimen Contamination of High-Performance EM

1977 ◽  
Vol 35 ◽  
pp. 68-69
Author(s):  
N. Yoshimura ◽  
K. Shirota ◽  
T. Etoh
Keyword(s):  
Electron Microscope ◽  
High Speed ◽  
High Performance ◽  
High Vacuum ◽  
Vacuum System ◽  
Pump System ◽  
Pumping System ◽  
Diffusion Pump ◽  
Almost All ◽  
Cascade Type

One of the most important requirements for a high-performance EM, especially an analytical EM using a fine beam probe, is to prevent specimen contamination by providing a clean high vacuum in the vicinity of the specimen. However, in almost all commercial EMs, the pressure in the vicinity of the specimen under observation is usually more than ten times higher than the pressure measured at the punping line. The EM column inevitably requires the use of greased Viton O-rings for fine movement, and specimens and films need to be exchanged frequently and several attachments may also be exchanged. For these reasons, a high speed pumping system, as well as a clean vacuum system, is now required. A newly developed electron microscope, the JEM-100CX features clean high vacuum in the vicinity of the specimen, realized by the use of a CASCADE type diffusion pump system which has been essentially improved over its predeces- sorD employed on the JEM-100C.

PHAX-SCAN: Functional integration of a Scanning Electron Microscope and an energy-dispersive x-ray analyser

1989 ◽  
Vol 47 ◽  
pp. 56-57
Author(s):  
Marc H. Peeters ◽  
Max T. Otten
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
High Speed ◽  
High Performance ◽  
Functional Integration ◽  
Energy Dispersive ◽  
X Rays ◽  
X Ray ◽  
High Speed Analysis ◽  
Scanning Electron

Over the past decades, the combination of energy-dispersive analysis of X-rays and scanning electron microscopy has proved to be a powerful tool for fast and reliable elemental characterization of a large variety of specimens. The technique has evolved rapidly from a purely qualitative characterization method to a reliable quantitative way of analysis. In the last 5 years, an increasing need for automation is observed, whereby energy-dispersive analysers control the beam and stage movement of the scanning electron microscope in order to collect digital X-ray images and perform unattended point analysis over multiple locations.The Philips High-speed Analysis of X-rays system (PHAX-Scan) makes use of the high performance dual-processor structure of the EDAX PV9900 analyser and the databus structure of the Philips series 500 scanning electron microscope to provide a highly automated, user-friendly and extremely fast microanalysis system. The software that runs on the hardware described above was specifically designed to provide the ultimate attainable speed on the system.

The bright future of digital imaging in scanning electron microscopy

1993 ◽  
Vol 51 ◽  
pp. 768-769
Author(s):  
M. T. Postek ◽  
A. E. Vladar
Keyword(s):  
Electron Microscopy ◽  
Scanning Electron Microscopy ◽  
Digital Imaging ◽  
High Speed ◽  
High Performance ◽  
Mass Storage ◽  
Analog To Digital ◽  
Central Processing ◽  
Digital Imaging Technology ◽  
Scanning Electron

One of the major advancements applied to scanning electron microscopy (SEM) during the past 10 years has been the development and application of digital imaging technology. Advancements in technology, notably the availability of less expensive, high-density memory chips and the development of high speed analog-to-digital converters, mass storage and high performance central processing units have fostered this revolution. Today, most modern SEM instruments have digital electronics as a standard feature. These instruments, generally have 8 bit or 256 gray levels with, at least, 512 × 512 pixel density operating at TV rate. In addition, current slow-scan commercial frame-grabber cards, directly applicable to the SEM, can have upwards of 12-14 bit lateral resolution permitting image acquisition at 4096 × 4096 resolution or greater. The two major categories of SEM systems to which digital technology have been applied are:In the analog SEM system the scan generator is normally operated in an analog manner and the image is displayed in an analog or "slow scan" mode.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

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