scholarly journals HARDWARE IMPLEMENTATION OF AN ENCRYPTION FOR ENHANCEMENT DGHV

2019 ◽  
Vol 2 (2) ◽  
pp. 44-57
Author(s):  
Zainab H. Mahmood ◽  
Mahmood K. Ibrahem
Keyword(s):  
Real Time ◽  
High Speed ◽  
Hardware Implementation ◽  
Graphics Processing Unit ◽  
Homomorphic Encryption ◽  
Processing Unit ◽  
Fully Homomorphic Encryption ◽  
Encryption Schemes ◽  
Field Programmable ◽  
Programmable Gate Arrays

In constructing a secure and reliable cloud computing environment, a fully homomorphic encryption (FHE) scheme is conceived as a major cryptographic tool, as it enables arbitrary arithmetic evaluation of a cipher text without revealing the plaintext. However, due to very high of fully homomorphic encryption systems stays impractical and unfit for real-time applications  One way to address this restriction is by using graphics processing unit (GPUs) and field programmable gate arrays (FPGAs) to produce homomorphic encryption schemes. This paper represents the hardware implementation of an encryption for enhancement van Dijk, Gentry, Halevi and Vaikuntanathan’s (DGHV) scheme over the integer (DGHV10) using FPGA technology for high speed computation and real time results. The proposed method was simulated via Vivado system generator tools. Then design systems of fully homomrphic encryption are implemented in an FPGA hardware successfully using NEXYS 4 DDR board with ARTIX 7 XC7A100T FPGA. The Experimental results show that the FPGA- based fully homomorphic encryption system is 63 times faster than the simulation based implementation.

scholarly journals Embedded GPU Implementation for High-Performance Ultrasound Imaging

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 884
Author(s):  
Stefano Rossi ◽  
Enrico Boni
Keyword(s):  
High Performance ◽  
Graphics Processing Unit ◽  
Digital Signal ◽  
Processing Unit ◽  
Embedded Computing ◽  
Field Programmable ◽  
Peripheral Component Interconnect ◽  
Programmable Gate Arrays ◽  
Graphics Processing ◽  
Signal Processors

Methods of increasing complexity are currently being proposed for ultrasound (US) echographic signal processing. Graphics Processing Unit (GPU) resources allowing massive exploitation of parallel computing are ideal candidates for these tasks. Many high-performance US instruments, including open scanners like ULA-OP 256, have an architecture based only on Field-Programmable Gate Arrays (FPGAs) and/or Digital Signal Processors (DSPs). This paper proposes the implementation of the embedded NVIDIA Jetson Xavier AGX module on board ULA-OP 256. The system architecture was revised to allow the introduction of a new Peripheral Component Interconnect Express (PCIe) communication channel, while maintaining backward compatibility with all other embedded computing resources already on board. Moreover, the Input/Output (I/O) peripherals of the module make the ultrasound system independent, freeing the user from the need to use an external controlling PC.

scholarly journals Real-Time Monte Carlo Optimization on FPGA for the Efficient and Reliable Message Chain Structure

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 866 ◽  
Author(s):  
Heoncheol Lee ◽  
Kipyo Kim
Keyword(s):  
Monte Carlo ◽  
Real Time ◽  
Communication Systems ◽  
Optimization Method ◽  
Chain Structure ◽  
Processing Unit ◽  
Monte Carlo Optimization ◽  
Central Processing ◽  
Field Programmable ◽  
Programmable Gate Arrays

This paper addresses the real-time optimization problem to find the most efficient and reliable message chain structure in data communications based on half-duplex command–response protocols such as MIL-STD-1553B communication systems. This paper proposes a real-time Monte Carlo optimization method implemented on field programmable gate arrays (FPGA) which can not only be conducted very quickly but also avoid the conflicts with other tasks on a central processing unit (CPU). Evaluation results showed that the proposed method can consistently find the optimal message chain structure within a quite small and deterministic time, which was much faster than the conventional Monte Carlo optimization method on a CPU.

scholarly journals ICE-Based Custom Full-Mesh Network for the CHIME High Bandwidth Radio Astronomy Correlator

2016 ◽  
Vol 05 (04) ◽  
pp. 1641004 ◽  
Author(s):  
K. Bandura ◽  
J. F. Cliche ◽  
M. A. Dobbs ◽  
A. J. Gilbert ◽  
D. Ittah ◽  
...  
Keyword(s):  
High Speed ◽  
Graphics Processing Unit ◽  
Mesh Network ◽  
Processing Unit ◽  
Intensity Mapping ◽  
Large Bandwidth ◽  
Data Links ◽  
Data Rates ◽  
Combining Data ◽  
Field Programmable

New generation radio interferometers encode signals from thousands of antenna feeds across large bandwidth. Channelizing and correlating this data requires networking capabilities that can handle unprecedented data rates with reasonable cost. The Canadian Hydrogen Intensity Mapping Experiment (CHIME) correlator processes 8-bits from [Formula: see text] digitizer inputs across 400[Formula: see text]MHz of bandwidth. Measured in [Formula: see text] bandwidth, it is the largest radio correlator that is currently commissioning. Its digital back-end must exchange and reorganize the 6.6[Formula: see text]terabit/s produced by its 128 digitizing and channelizing nodes, and feed it to the 256 graphics processing unit (GPU) node spatial correlator in a way that each node obtains data from all digitizer inputs but across a small fraction of the bandwidth (i.e. ‘corner-turn’). In order to maximize performance and reliability of the corner-turn system while minimizing cost, a custom networking solution has been implemented. The system makes use of Field Programmable Gate Array (FPGA) transceivers to implement direct, passive copper, full-mesh, high speed serial connections between sixteen circuit boards in a crate, to exchange data between crates, and to offload the data to a cluster of 256 GPU nodes using standard 10[Formula: see text]Gbit/s Ethernet links. The GPU nodes complete the corner-turn by combining data from all crates and then computing visibilities. Eye diagrams and frame error counters confirm error-free operation of the corner-turn network in both the currently operating CHIME Pathfinder telescope (a prototype for the full CHIME telescope) and a representative fraction of the full CHIME hardware providing an end-to-end system validation. An analysis of an equivalent corner-turn system built with Ethernet switches instead of custom passive data links is provided.

HARDWARE IMPLEMENTATION OF STOCHASTIC SPIKING NEURAL NETWORKS

2012 ◽  
Vol 22 (04) ◽  
pp. 1250014 ◽  
Author(s):  
JOSEP L. ROSSELLÓ ◽  
VINCENT CANALS ◽  
ANTONI MORRO ◽  
ANTONI OLIVER
Keyword(s):  
Neural Networks ◽  
High Speed ◽  
Hardware Implementation ◽  
Linear Equations ◽  
Spiking Neural Networks ◽  
Proposed Model ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Systems Of Linear Equations ◽  
Probabilistic Nature

Spiking Neural Networks, the last generation of Artificial Neural Networks, are characterized by its bio-inspired nature and by a higher computational capacity with respect to other neural models. In real biological neurons, stochastic processes represent an important mechanism of neural behavior and are responsible of its special arithmetic capabilities. In this work we present a simple hardware implementation of spiking neurons that considers this probabilistic nature. The advantage of the proposed implementation is that it is fully digital and therefore can be massively implemented in Field Programmable Gate Arrays. The high computational capabilities of the proposed model are demonstrated by the study of both feed-forward and recurrent networks that are able to implement high-speed signal filtering and to solve complex systems of linear equations.

USING FIELD-PROGRAMMABLE GATE ARRAYS FOR HIGH-SPEED REAL-TIME SIMULATION

2010 ◽  
Vol 01 (01) ◽  
pp. 99-115 ◽  
Author(s):  
ROY CROSBIE
Keyword(s):  
Real Time ◽  
High Speed ◽  
Digital Signal ◽  
Field Programmable Gate Arrays ◽  
Electronic Systems ◽  
Real Time Simulation ◽  
Gate Arrays ◽  
Time Simulation ◽  
Field Programmable ◽  
Programmable Gate Arrays

Some applications of real-time simulation now require frame times that are shorter in duration than can be delivered by traditional methods such as real-time versions of Linux (RT-Linux). RT-Linux can be satisfactory for frames as short as 10μS, but there is now a need, for example in the simulation of power-electronic systems, for frame times as short as 1 μS or even less. Techniques based on the interfacing of digital signal processors (DSPs) to a Windows PC have achieved a 2 μS frame time for a typical power electronics application and less than 1 μS is shown to be possible using field-programmable gate arrays (FPGAs). Combining these high-speed techniques with simulations of the rest of the system necessitates the use of multi-rate techniques. Software tools, interfacing issues, and system architecture for a high-speed, real-time, distributed, multi-rate (HRDM) simulator are discussed.

Accelerating laser processes with a smart two-dimensional polygon mirror scanner for ultra-fast beam deflection

2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Florian Roessler ◽  
André Streek
Keyword(s):  
Energy Distribution ◽  
Real Time ◽  
Laser Processing ◽  
High Speed ◽  
Beam Deflection ◽  
Two Dimensional ◽  
Heat Accumulation ◽  
Field Programmable ◽  
Drill Holes ◽  
Average Laser

Abstract In laser processing, the possible throughput is directly scaling with the available average laser power. To avoid unwanted thermal damage due to high pulse energy or heat accumulation during MHz-repetition rates, energy distribution over the workpiece is required. Polygon mirror scanners enable high deflection speeds and thus, a proper energy distribution within a short processing time. The requirements of laser micro processing with up to 10 kW average laser powers and high scan speeds up to 1000 m/s result in a 30 mm aperture two-dimensional polygon mirror scanner with a patented low-distortion mirror configuration. In combination with a field programmable gate array-based real-time logic, position-true high-accuracy laser switching is enabled for 2D, 2.5D, or 3D laser processing capable to drill holes in multi-pass ablation or engraving. A special developed real-time shifter module within the high-speed logic allows, in combination with external axis, the material processing on the fly and hence, processing of workpieces much larger than the scan field.

Real-time, High-resolution Depth Upsampling on Embedded Accelerators

2021 ◽  
Vol 20 (3) ◽  
pp. 1-22
Author(s):  
David Langerman ◽  
Alan George
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Real Time ◽  
Mixed Reality ◽  
Graphics Processing Unit ◽  
Processing Unit ◽  
Reconfigurable Logic ◽  
Depth Sensors ◽  
Time Requirements ◽  
Graphics Processing

High-resolution, low-latency apps in computer vision are ubiquitous in today’s world of mixed-reality devices. These innovations provide a platform that can leverage the improving technology of depth sensors and embedded accelerators to enable higher-resolution, lower-latency processing for 3D scenes using depth-upsampling algorithms. This research demonstrates that filter-based upsampling algorithms are feasible for mixed-reality apps using low-power hardware accelerators. The authors parallelized and evaluated a depth-upsampling algorithm on two different devices: a reconfigurable-logic FPGA embedded within a low-power SoC; and a fixed-logic embedded graphics processing unit. We demonstrate that both accelerators can meet the real-time requirements of 11 ms latency for mixed-reality apps. 1

scholarly journals Electronic Orientation Aid for Visually Impaired using Graphics Processing Unit (GPU)

2020 ◽  
Vol 32 ◽  
pp. 03054
Author(s):  
Akshata Parab ◽  
Rashmi Nagare ◽  
Omkar Kolambekar ◽  
Parag Patil
Keyword(s):  
Real Time ◽  
Visually Impaired ◽  
Graphics Processing Unit ◽  
Human Perception ◽  
Processing Unit ◽  
Surrounding Environment ◽  
Visually Impaired People ◽  
Impaired People ◽  
Definition Of ◽  
Graphics Processing

Vision is one of the very essential human senses and it plays a major role in human perception about surrounding environment. But for people with visual impairment their definition of vision is different. Visually impaired people are often unaware of dangers in front of them, even in familiar environment. This study proposes a real time guiding system for visually impaired people for solving their navigation problem and to travel without any difficulty. This system will help the visually impaired people by detecting the objects and giving necessary information about that object. This information may include what the object is, its location, its precision, distance from the visually impaired etc. All these information will be conveyed to the person through audio commands so that they can navigate freely anywhere anytime with no or minimal assistance. Object detection is done using You Only Look Once (YOLO) algorithm. As the process of capturing the video/images and sending it to the main module has to be carried at greater speed, Graphics Processing Unit (GPU) is used. This will help in enhancing the overall speed of the system and will help the visually Impaired to get the maximum necessary instructions as quickly as possible. The process starts from capturing the real time video, sending it for analysis and processing and get the calculated results. The results obtained from analysis are conveyed to user by means of hearing aid. As a result by this system the blind or the visually impaired people can visualize the surrounding environment and travel freely from source to destination on their own.

scholarly journals Real-time speckle variance swept-source optical coherence tomography using a graphics processing unit

2012 ◽  
Vol 3 (7) ◽  
pp. 1557 ◽  
Author(s):  
Kenneth K. C. Lee ◽  
Adrian Mariampillai ◽  
Joe X. Z. Yu ◽  
David W. Cadotte ◽  
Brian C. Wilson ◽  
...  
Keyword(s):  
Optical Coherence Tomography ◽  
Real Time ◽  
Graphics Processing Unit ◽  
Processing Unit ◽  
Optical Coherence ◽  
Swept Source ◽  
Graphics Processing
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