scholarly journals Design of Parallel Image Compression Circuits for High-speed CMOS Image Sensors

2007 ◽  
Vol 61 (3) ◽  
pp. 369-377
Author(s):  
Yukinari Nishikawa ◽  
Shoji Kawahito ◽  
Masanori Furuta ◽  
Toshihiro Tamura
Keyword(s):  
Image Compression ◽  
High Speed ◽  
Image Sensors ◽  
Parallel Image ◽  
Cmos Image Sensors

Parallel image compression circuit for high-speed cameras

2005 ◽  
Author(s):  
Yukinari Nishikawa ◽  
Shoji Kawahito ◽  
Toru Inoue
Keyword(s):  
Image Compression ◽  
High Speed ◽  
Parallel Image

Current Sensing-Assisted Active Pixel Sensor for High-Speed CMOS Image Sensors

2015 ◽  
Vol 15 (8) ◽  
pp. 4365-4372
Author(s):  
Swetha S. George ◽  
Mark F. Bocko ◽  
Zeljko Ignjatovic
Keyword(s):  
High Speed ◽  
Image Sensors ◽  
Current Sensing ◽  
Active Pixel Sensor ◽  
Cmos Image Sensors ◽  
Active Pixel

A 10-Bit Column-Parallel Single Slope ADC Based on Two-Step TDC with Error Calibration for CMOS Image Sensors

2015 ◽  
Vol 24 (04) ◽  
pp. 1550054 ◽  
Author(s):  
Jiangtao Xu ◽  
Jing Yu ◽  
Fujun Huang ◽  
Kaiming Nie
Keyword(s):  
Analog Circuits ◽  
High Speed ◽  
Propagation Delay ◽  
Image Sensors ◽  
Time Interval ◽  
Cmos Process ◽  
Digital Converter ◽  
Cmos Image Sensors ◽  
Time Problem ◽  
The Impact

This paper presents a 10-bit column-parallel single slope analog-to-digital converter (SS ADC) with a two-step time-to-digital converter (TDC) to overcome the long conversion time problem in conventional SS ADC for high-speed CMOS image sensors (CIS). The time interval proportional to the input signal is generated by a ramp generator and a comparator, which is digitized by a two-step TDC consisting of coarse and fine conversions to achieve a high-precision time-interval measurement. To mitigate the impact of propagation delay mismatch, a calibration circuit is also proposed to calibrate the delay skew within -T/2 to T/2. The proposed ADC is designed in 0.18 μm CMOS process. The power dissipation of each column circuit is 232 μW at supply voltages of 3.3 V for the analog circuits and 1.8 V for the digital blocks. The post simulation results indicate that the ADC achieves a SNDR of 60.89 dB (9.82 ENOB) and a SFDR of 79.98 dB at a conversion rate of 2 MS/s after calibration, while the SNDR and SFDR are limited to 41.52 dB and 67.64 dB, respectively before calibration. The differential nonlinearity (DNL) and integral nonlinearity (INL) without calibration are +15.80/-15.29 LSB and +1.68/-15.34 LSB while they are reduced down to +0.75/-0.25 LSB and +0.76/-0.78 LSB with the proposed calibration.

A 12-bit compact column-parallel SAR ADC with dynamic power control technique for high-speed CMOS image sensors

2014 ◽  
Vol 35 (10) ◽  
pp. 105008
Author(s):  
Quanliang Li ◽  
Liyuan Liu ◽  
Ye Han ◽  
Zhongxiang Cao ◽  
Nanjian Wu
Keyword(s):  
Power Control ◽  
High Speed ◽  
Image Sensors ◽  
Sar Adc ◽  
Control Technique ◽  
Dynamic Power ◽  
Cmos Image Sensors

scholarly journals PETAL: A Multichannel Differential ADC Driver for High-Speed CMOS Image Sensors

2019 ◽  
Vol 66 (6) ◽  
pp. 955-959
Author(s):  
C. R. Grace ◽  
T. Stezelberger ◽  
P. Denes
Keyword(s):  
High Speed ◽  
Image Sensors ◽  
Cmos Image Sensors
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