Boundary-Scan’s Next Plateau: Testing and In-System Configuration at the System Level

Author(s):  
Pete Collins ◽  
Ray Dellecker

Abstract Boundary-scan is a technology that’s been around for over ten years and is delivering the results foreseen by the IEEE working group that developed the 1149.1 specification. Many SMT (surface mount) production lines around the world use boundary-scan to solve the testing challenges presented by today’s complex designs. These users are realizing the vision of the specification, using it to restore test access and fault coverage to assemblies with few physical test points relative to the number of electrical nets to be tested. As the boundary-scan standard has gained acceptance and credibility, users, chip vendors and tools providers have developed important extensions of the original vision. Among the extensions already available or under active consideration is the use of boundary-scan for analog testing, concurrent programming of multi-vendor cPLD’s, dynamic verification of high-speed communication channels, and application within higher-level electronic assemblies beyond printed circuit boards i.e. to subsystems and systems. This paper describes the effectiveness of boundaryscan at the system level, focusing on the use of IEEE Std. 1149.1 compatible devices and ATPG tools to accomplish system level testing and in-system configuration.

1999 ◽  
Vol 11 (2) ◽  
pp. 104-111
Author(s):  
Toshifumi Honda ◽  
◽  
Hisae Yamamura ◽  
Mineo Nomoto ◽  
Takanori Ninomiya ◽  
...  

Automated visual solder inspection was studied for different printed circuit boards (PCBs) based on 3-D-image analysis. The optical 3-D scanner accurately detects height of a solder joint from differently focused images of a laser spot. Emitted laser light on the solder joint is detected simultaneously by plural sensors whose focal points are set at different height to realize high-speed height acquisition without secondary-reflection problems caused by the specular surface of the solder joint. An inspection algorithm was designed to recognize a solder joint using detected height and the intensity image so that different shapes of solder fillet do not affect inspection performance. A solder joint is classified based on extracted 3-D features of its fillet shape and 3-D location of the lead from its pad. Inspection parameters are automatically generated with inspection parameter autogeneration using electronic component and PCB design data. Evaluation showed the system gave 100% defect detection and very few false alarms (0.13%) using autogenerated inspection parameters. Results show the technique to be promising in actual production lines for different PCBs.


2010 ◽  
Vol 2010 (1) ◽  
pp. 000413-000421 ◽  
Author(s):  
Steven G. Pytel ◽  
Scott C. McMorrow ◽  
Tom Dagostino ◽  
Sergey Polstyanko ◽  
Werner Thiel ◽  
...  

The aim of this work is to provide strategies for creating highly accurate models of printed circuit boards (PCBs) and substrates using electromagnetic field solvers. It will examine how to choose the correct field solver for a particular application from among full-wave, modal decomposition, finite element and boundary element methods. Tradeoffs between time and accuracy of the different solvers will be discussed. The focus is on model creation for use in time domain circuit simulators, but analysis of the frequency domain data will be used to correlate measurement to simulation. The problem of correlating simulation results with measurements is also discussed. A physical layer reference design (PLRD) board has been constructed, measured and simulated with the various field solvers. The results are analyzed to understand why differences occur between simulation and measured data. The impacts of these differences on system-level simulations of high-speed serial links are studied using a circuit simulator.


Author(s):  
S.V. Palochkin ◽  
Y.V. Sinitsyna ◽  
K.G. Erastova

The increased accuracy in high-speed positioning of the parallel robot effector in comparison with that of serial robots with a sequential structure is often the main reason for their use in various modern industries, such as the manufacture of printed circuit boards for microelectronics. However, despite the higher theoretical positioning accuracy, due to the kinematic structure of the parallel robot, in practice this characteristic largely depends on the accuracy of manufacturing individual elements of this mechanism, the most important of which are the gearboxes of the drives of its input pairs. A solution to the urgent problem of determining the effect of the manufacturing accuracy of planetary pinion gearboxes included in the drive of a five-link parallel robot on the positioning accuracy of its output link is proposed. A specific relationship has been determined between the grade of accuracy number of the gear part dimensions and the robot positioning accuracy. The unevenness of the positioning accuracy along the coordinate axes of its working area is revealed. It was found that near the area of certain robot positions the accuracy of its positioning drops sharply.


2018 ◽  
Vol 2018 (1) ◽  
pp. 000305-000309 ◽  
Author(s):  
Shiro Tatsumi ◽  
Shohei Fujishima ◽  
Hiroyuki Sakauchi

Abstract Build-up process is a highly effective method for miniaturization and high density integration of printed circuit boards. Along with increasing demands for high transmission speed of electronic devices with high functionality, packaging substrates installed with semiconductors in such devices are strongly required to reduce the transmission loss. Our insulation materials are used in a semi-additive process (SAP) with low dielectric loss tangent, smooth resin surface after desmear, and good insulation reliability. Actually, the transmission loss of strip line substrates and Cu surface roughness impact on transmission loss were measured using our materials. Furthermore, low dielectric molding film with low coefficient of thermal expansion (CTE) and low Young's modulus are introduced.


Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1473
Author(s):  
Aleksandr Vasjanov ◽  
Vaidotas Barzdenas

In the era of technology and communication, printed circuit boards (PCBs) can be found in a myriad of devices—from ordinary household items, to state of the art custom metrology equipment. Different types of component for wireless communications are available and come in various packages, supplied by multiple manufacturers. The signal landpads for some high-frequency connectors and components, encapsulated in larger packages, are usually wider than the controlled impedance trace, thereby introducing unwanted impedance mismatch and resulting in signal reflections. The component land pad and microstrip width a discrepancy issue can be found in both complex high-density industrial devices and system-level academic research papers. This paper addresses the topic of compensating discontinuities, introduced by signal pads, which are wider than the target impedance microstrip, characterizes the difference between the compensated and uncompensated microstrip with discontinuity, and proposes a generalized guideline on compensating for the introduced impedance change in multilayer PCBs. The compensation method is based upon carefully designing the stackup of the PCB allowing for a reference plane cutout under the discontinuity to even out the impedance mismatch. A 6-layer PCB with IT180A dielectric material containing three structures has been manufactured and characterized using an Agilent E8363B vector network analyzer (VNA). A 4–12 dB improvement in S11 response in the whole frequency range up to 10 GHz, compared to that when no compensation has been applied, was observed.


Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 299 ◽  
Author(s):  
Myunghoi Kim

An analytical model for metamaterial differential transmission lines (MTM-DTLs) with a corrugated ground-plane electromagnetic bandgap (CGP-EBG) structure in high-speed printed circuit boards is proposed. The proposed model aims to efficiently and accurately predict the suppression of common-mode noise and differential signal transmission characteristics. Analytical expressions for the four-port impedance matrix of the CGP-EBG MTM-DTL are derived using coupled-line theory and a segmentation method. Converting the impedance matrix into mixed-mode scattering parameters enables obtaining common-mode noise suppression and differential signal transmission characteristics. The comprehensive evaluations of the CGP-EBG MTM-DTL using the proposed analytical model are also reported, which is validated by comparing mixed-mode scattering parameters Scc21 and Sdd21 with those obtained from full-wave simulations and measurements. The proposed analytical model provides a drastic reduction of computation time and accurate results compared to full-wave simulation.


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