scholarly journals Design of Double-Precision Floating-Point Division and Square Root Based on SRT Algorithm

2014 ◽  
Author(s):  
Jiyang Chen ◽  
Yuanxi Peng ◽  
Yuanwu Lei ◽  
Ziye Deng
Keyword(s):  
Floating Point ◽  
Double Precision ◽  
Square Root

Double Precision Floating Point Square Root Computation

2014 ◽  
Vol 13 (6) ◽  
pp. 294-298
Author(s):  
Najib Ghatte ◽  
◽  
Shilpa Patil ◽  
Deepak Bhoir
Keyword(s):  
Floating Point ◽  
Double Precision ◽  
Square Root

An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation

2015 ◽  
Vol 24 (10) ◽  
pp. 1550151
Author(s):  
Wei Guo ◽  
KwangHyok Ri ◽  
Luping Cui ◽  
Jizeng Wei
Keyword(s):  
Logic Gates ◽  
Lookup Table ◽  
Floating Point ◽  
Cmos Process ◽  
Double Precision ◽  
Square Root ◽  
Area Efficiency ◽  
Area Reduction ◽  
Efficiency Performance ◽  
Performance Area

In this paper, we propose a unified architecture for computation of double-precision floating-point division, reciprocal, square root, inverse square root and multiplication with a significant area reduction. First, a double-precision multiplication-based divider, the common datapath shared with these arithmetic computations, is optimized by a modified Goldschmidt algorithm to achieve better area efficiency. In this algorithm, a linear-degree minimax approximation instead of second-degree is used to obtain a 15-bit precision estimate of the reciprocal so that we can get a rather small lookup table (LUT) as well as reduced amount of computation when accumulating the partial products. Two Goldschmidt iterations specially designed for hardware reuse are performed to gain the final accurate result of division. By virtue of the pipelined processing, the time cost for the two iterations is minimized. Second, a reconfigurable datapath with a little extra area cost is introduced to dynamically support multiple double-precision computations by executing the optimized divider iteratively. The design is finally implemented and synthesized in SMIC 0.13-μm CMOS process. The experimental results show that the proposed design can achieve a speed of 400 MHz with area of 61.6 K logic gates and 9-Kb LUT. Compared with other works, the area efficiency (performance/area ratio) of the proposed unified architecture is increased by about 20% in average, which is a better performance-area trade-off for embedded microprocessors.

scholarly journals Modified Fast Inverse Square Root and Square Root Approximation Algorithms: The Method of Switching Magic Constants

Computation ◽  
2021 ◽  
Vol 9 (2) ◽  
pp. 21 ◽  
Author(s):  
Leonid V. Moroz ◽  
Volodymyr V. Samotyy ◽  
Oleh Y. Horyachyy
Keyword(s):  
Low Cost ◽  
Initial Approximation ◽  
Floating Point ◽  
Maximum Relative Error ◽  
Double Precision ◽  
Square Root ◽  
Simple Modification ◽  
Field Programmable ◽  
Complex Solutions ◽  
Good Trade

Many low-cost platforms that support floating-point arithmetic, such as microcontrollers and field-programmable gate arrays, do not include fast hardware or software methods for calculating the square root and/or reciprocal square root. Typically, such functions are implemented using direct lookup tables or polynomial approximations, with a subsequent application of the Newton–Raphson method. Other, more complex solutions include high-radix digit-recurrence and bipartite or multipartite table-based methods. In contrast, this article proposes a simple modification of the fast inverse square root method that has high accuracy and relatively low latency. Algorithms are given in C/C++ for single- and double-precision numbers in the IEEE 754 format for both square root and reciprocal square root functions. These are based on the switching of magic constants in the initial approximation, depending on the input interval of the normalized floating-point numbers, in order to minimize the maximum relative error on each subinterval after the first iteration—giving 13 correct bits of the result. Our experimental results show that the proposed algorithms provide a fairly good trade-off between accuracy and latency after two iterations for numbers of type float, and after three iterations for numbers of type double when using fused multiply–add instructions—giving almost complete accuracy.

scholarly journals Research on IEEE 754 Standard Single Precision Floating Point Multipliers Designed using Urdhva Triyagbhyam Sutra of Vedic Mathematics

2019 ◽  
Vol 8 (2S11) ◽  
pp. 2990-2993
Keyword(s):  
Floating Point ◽  
Double Precision ◽  
Single Precision ◽  
Vedic Mathematics ◽  
Quadruple Precision

Duplication of the coasting element numbers is the big activity in automated signal handling. So the exhibition of drifting problem multipliers count on a primary undertaking in any computerized plan. Coasting factor numbers are spoken to utilizing IEEE 754 modern day in single precision(32-bits), Double precision(sixty four-bits) and Quadruple precision(128-bits) organizations. Augmentation of those coasting component numbers can be completed via using Vedic generation. Vedic arithmetic encompass sixteen wonderful calculations or Sutras. Urdhva Triyagbhyam Sutra is most usually applied for growth of twofold numbers. This paper indicates the compare of tough work finished via exceptional specialists in the direction of the plan of IEEE 754 ultra-modern-day unmarried accuracy skimming thing multiplier the usage of Vedic technological statistics.

DPF-ECC: A Framework for Efficient ECC with Double Precision Floating-Point Computing Power

2021 ◽  
pp. 1-1
Author(s):  
Lili Gao ◽  
Fangyu Zheng ◽  
Rong Wei ◽  
Jiankuo Dong ◽  
Niall Emmart ◽  
...  
Keyword(s):  
Floating Point ◽  
Double Precision ◽  
Computing Power
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