scholarly journals Efficient area optimization in high level synthesis using priority-driven simulated annealing. (c2009)

2009 ◽  
Author(s):  
Maria Abi Saad
Keyword(s):  
Simulated Annealing ◽  
High Level Synthesis ◽  
Area Optimization ◽  
High Level

PRIORITY-DRIVEN AREA OPTIMIZATION IN HIGH-LEVEL SYNTHESIS

2011 ◽  
Vol 20 (06) ◽  
pp. 1131-1163
Author(s):  
MARIA ABI SAAD ◽  
IYAD OUAISS
Keyword(s):  
Simulated Annealing ◽  
Execution Time ◽  
Annealing Process ◽  
Optimization Techniques ◽  
High Level Synthesis ◽  
Area Reduction ◽  
Area Optimization ◽  
Functional Units ◽  
Priority Function ◽  
High Level

One of the major enhancements that can be made to the high-level synthesis (HLS) process is reducing the overall area of a design in order to either decrease the manufacturing costs or to introduce more functionality to the circuit. Optimizing the area of the datapath is considered a primary field of research in HLS. This work proposes an approach to reduce the area in field programmable gate array (FPGA) by simultaneously tackling the three central tasks of HLS. Scheduling, allocation, and binding are performed and the optimal solution based on area reduction is obtained by using simulated annealing with a priority function. The aim of the priority function is to guide the simulated annealing process into finding the best solution while at the same time incurring the least possible execution time. In order to achieve better results than the initial solution, rescheduling, swapping operations between functional units, swapping variables between registers, and swapping inputs to functional units are considered in the annealing process. A cost function is devised to evaluate a potential move's success or failure. The simulation environment "Eridanus" has been developed in order to support implementation and testing. Several benchmarks were tested and the numerical results consisting of the execution time along with the best solution were recorded to illustrate the performance of the proposed technique. Area reduction was obtained compared to the conventional HLS flow; furthermore, an average substantial reduction in design space exploration time was obtained compared to non-priority based area optimization techniques.

Area Optimization of Combined Integer and Floating Point Circuits in High-Level Synthesis

2008 ◽  
Author(s):  
Esther Andres ◽  
Maria C. Molina ◽  
Guillermo Botella ◽  
Alberto del Barrio ◽  
Jose M. Mendias
Keyword(s):  
High Level Synthesis ◽  
Floating Point ◽  
Area Optimization ◽  
High Level

A Power-Driven Stochastic-Deterministic Hierarchical High-Level Synthesis Framework for Module Selection, Scheduling and Binding

2019 ◽  
Vol 15 (4) ◽  
pp. 388-409
Author(s):  
Xiuyan Zhang ◽  
Ouwen Shi ◽  
Jian Xu ◽  
Shantanu Dutt
Keyword(s):  
Simulated Annealing ◽  
Scheduling Algorithm ◽  
Solution Space ◽  
Leakage Power ◽  
High Level Synthesis ◽  
Problem Solution ◽  
List Scheduling ◽  
Hierarchical Framework ◽  
Module Selection ◽  
High Level

We present a power-driven hierarchical framework for module/functional-unit selection, scheduling, and binding in high level synthesis. A significant aspect of algorithm design for large and complex problems is arriving at tradeoffs between quality of solution and timing complexity. Towards this end, we integrate an improved version of the very runtime-efficient list scheduling algorithm called modified list scheduling (MLS) with a power-driven simulated annealing (SA) algorithm for module selection. Our hierarchical framework efficiently explores the problem solution space by an extensive exploration of the power-driven module-selection solution space via SA, and for each module selection solution, uses MLS to obtain a scheduling and (integrated) binding (S&B) solution in which the binding is either a regular one (minimizing number of FUs and thus FU leakage power) or power-driven with mux/demux power considerations. This framework avoids the very runtime intensive exploration of both module selection and S&B within a conventional SA algorithm, but retains the basic prowess of SA by exploring only the important aspect of power-driven module-selection in a stochastic manner. The proposed hierarchical framework provides an average of 9.5% FU leakage power improvement over state of the art (approximate) algorithms that optimize only FU leakage power, and has a smaller runtime by factors of 2.5–3x. Further, compared to a sophisticated flat simulated annealing framework and an optimal 0/1-ILP formulation for total (dynamic and leakage) FU and architecture power optimization under latency constraints, PSA-MLS provides an improvement of 5.3–5.8% with a runtime advantage of 2x, and has an average optimality gap of only 4.7–4.8% with a significant runtime advantage of a factor of more than 1900, respectively.

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

2009 ◽  
Vol E92-A (12) ◽  
pp. 3169-3179 ◽  
Author(s):  
Akira OHCHI ◽  
Nozomu TOGAWA ◽  
Masao YANAGISAWA ◽  
Tatsuo OHTSUKI
Keyword(s):  
High Level Synthesis ◽  
High Level
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