A 65�A 8MHz Integrated Oscillator with LDO Regulator Supply for Low-Power Handheld SoC Applications

2008 ◽  
Vol 1 (4) ◽  
pp. 9-14
Author(s):  
Jacob Day ◽  
Paul Vulpoiu ◽  
Jeffery Julich ◽  
Donald Lie
Keyword(s):  
Low Power ◽  
Ldo Regulator

Low-Power Fast-Settling Low-Dropout Regulator Using a Digitally Assisted Voltage Accelerator for DVFS Application

2013 ◽  
Vol 284-287 ◽  
pp. 2526-2530
Author(s):  
Wei Ben Yang ◽  
Chi Hsiung Wang ◽  
Hsiang Hsiung Chang ◽  
Ming Hao Hong ◽  
Jsung Mo Shen
Keyword(s):  
Low Power ◽  
Output Voltage ◽  
Voltage Control ◽  
Control Unit ◽  
Settling Time ◽  
Control Technique ◽  
Dynamic Voltage ◽  
Low Dropout Regulator ◽  
Ldo Regulator ◽  
Fast Settling

This paper presents a low-power fast-settling low-dropout regulator (LDO) using a digitally assisted voltage accelerator. Using the selectable-voltage control technique and digitally assisted voltage accelerator significantly improves the transition response time within output voltage switched. The proposed LDO regulator uses the selectable-voltage control technique to provide two selectable-voltage outputs of 2.5 V and 1.8 V. Using the digitally assisted voltage accelerator when the output voltage is switched reduces the settling time. The simulation results show that the settling time of the proposed LDO regulator is significantly reduced from 4.2 ms to 15.5 μs. Moreover, the selectable-voltage control unit and the digitally assisted voltage accelerator of the proposed LDO regulator consume only 0.54 mW under a load current of 100 mA. Therefore, the proposed LDO regulator is suitable for low-power dynamic voltage and frequency-scaling applications.

scholarly journals Low power output-capacitorless class-AB CMOS LDO regulator

2017 ◽  
Author(s):  
Vahideh Shirmohammadli ◽  
Alireza Saberkari ◽  
Herminio Martinez-Garcia ◽  
Eduard Alarcon-Cot
Keyword(s):  
Low Power ◽  
Power Output ◽  
Class Ab ◽  
Ldo Regulator

scholarly journals Design of the low noise CMOS LDO regulator for a low power capacitivesensor interface

2010 ◽  
Vol 19 (1) ◽  
pp. 25-30 ◽  
Author(s):  
Bo-Min Kwon ◽  
Jin-Woo Jung ◽  
Ji-Man Kim ◽  
Yong-Su Park ◽  
Han-Jung Song
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Ldo Regulator

scholarly journals Nano-Power Low-Dropout Voltage Regulator Circuit in 90-nm CMOS Technology for RF SoC Applications

2021 ◽  
Vol 15 ◽  
pp. 240-248
Author(s):  
Hicham Akhamal ◽  
Mostafa Chakir ◽  
Hatim Ameziane ◽  
Mohammed Akhamal ◽  
Kamal Zared ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Cmos Technology ◽  
System On Chip ◽  
Drop Out ◽  
Voltage Regulator ◽  
Weak Inversion ◽  
Low Power Dissipation ◽  
On Chip ◽  
Ldo Regulator

This paper presents a nano-power Low Drop-Out (LDO) voltage regulator circuit for Radio-Frequency System-on-Chip (RF SoC) applications, this LDO is designed for a smaller dimension due to CMOS technology and in the weak inversion region, can thus be used to minimize power loss of LDO regulator without transientresponse degradation. The proposed structure its low power dissipation make it ideal for RF system-on-chip applications that require low power dissipation under different loading conditions. In order to optimize performance for LDO, the proposed amplifier helps to minimize power of LDO regulators without using any onchip and off-chip compensation capacitors. The output spot noise at 100Hz and 1 kHz are 200nV/sqrt (Hz) and 6nV/sqrt (Hz), respectively. The active area of the circuit is 850 µm2 . The regulator operates with supply voltages from 1.2V to 2V.

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