scholarly journals Magic state distillation at intermediate size

2018 ◽  
Vol 18 (1&2) ◽  
pp. 114-140
Author(s):  
Jeongwan Haah ◽  
Matthew B. Hastings ◽  
D. Poulin ◽  
D. Wecker
Keyword(s):  
Error Correction ◽  
Asymptotic Limit ◽  
Asymptotic Performance ◽  
Output Error ◽  
Size Regime ◽  
Intermediate Size ◽  
Input Error

Recently [1] we proposed a family of magic state distillation protocols that obtains asymptotic performance that is conjectured to be optimal. This family depends upon several codes, called “inner codes” and “outer codes.” In Ref. [1], some small examples of these codes were given as well as an analysis of codes in the asymptotic limit. Here, we analyze such protocols in an intermediate size regime, using hundreds to thousands of qubits. We use BCH inner codes [2], combined with various outer codes. We extend the protocols of Ref. [1] by adding error correction in some cases. We present a variety of protocols in various input error regimes; in many cases these protocols require significantly fewer input magic states to obtain a given output error than previous protocols.

On the Characteristics of the Autoassociative Memory with Nonzero-Diagonal Terms in the Memory Matrix

1991 ◽  
Vol 3 (3) ◽  
pp. 428-439 ◽  
Author(s):  
Jung-Hua Wang ◽  
Thomas F. Krile ◽  
John F. Walkup ◽  
Tai-Lang Jong
Keyword(s):  
Error Correction ◽  
Learning Algorithm ◽  
Attraction Force ◽  
Stable States ◽  
Outer Product ◽  
First Order ◽  
Error Correction Capability ◽  
Error Ratio ◽  
Successful Recall ◽  
Input Error

A statistical method is applied to explore the unique characteristics of a certain class of neural network autoassociative memory with N neurons and first-order synaptic interconnections. The memory matrix is constructed to store M = αN vectors based on the outer-product learning algorithm. We theoretically prove that, by setting all the diagonal terms of the memory matrix to be M and letting the input error ratio ρ = 0, the probability of successful recall Pr steadily decreases as α increases, but as α increases past 1.0, Pr begins to increase slowly. When 0 < ρ ≤ 0.5, the network exhibits strong error-correction capability if α ≤ 0.15 and this capability is shown to rapidly decrease as α increases. The network essentially loses all its error-correction capability at α = 2, regardless of the value of ρ. When 0 < ρ ≤ 0.5, and under the constraint of Pr > 0.99, the tradeoff between the number of stable states and their attraction force is analyzed and the memory capacity is shown to be 0.15N at best.

Study on the Decoder for Reed-Solomon (255, 239) Code

2013 ◽  
Vol 482 ◽  
pp. 390-393
Author(s):  
Yue Tao Ge ◽  
Xiao Ming Liu ◽  
Xiao Tong Yin
Keyword(s):  
Error Correction ◽  
Serial Port ◽  
Hardware Platform ◽  
Solomon Code ◽  
Serial Port Communication ◽  
Fast Speed ◽  
Error Correction Capability ◽  
Reed Solomon Code ◽  
To Receive ◽  
Input Error

Reed Solomon code is described as a theoretical decoder that corrected errors by finding the most popular message polynomial. The Verilog language is applied to descript decoding algorithm. Cyclone series FPGA EP1C6Q240C8 is adopted as a core of hardware platform and a serial port communication part is used to receive input error correction data. The results show that it can successfully correct eight errors, which is the limitation of error correction. With the RS decoder, it can ensure that the strong error correction capability and fast speed.

A novel approach of input tolerance design for parallel mechanisms using the level set method

2019 ◽  
Vol 234 (3) ◽  
pp. 371-381 ◽  
Author(s):  
Qiangqiang Zhao ◽  
Junkang Guo ◽  
Dewen Yu ◽  
Jun Hong ◽  
Zhigang Liu
Keyword(s):  
Level Set Method ◽  
Level Set ◽  
Degrees Of Freedom ◽  
Work Performance ◽  
Tolerance Design ◽  
Parallel Mechanisms ◽  
Output Error ◽  
Novel Approach ◽  
Normal Speed ◽  
Input Error

Input uncertainties inevitably result in the output error for parallel mechanisms, which will lead to significant influence on good work performance. To control the output error within the specification boundary, this article proposes a novel approach of input tolerance design based on the level set method for the driving joint. The implementation of the proposed method can be divided into two subtasks. First, using the level set method, the exact input error boundary is determined by means of evolving an initial input error interface with a defined normal speed field, thereby transforming the problem of exploring the exact boundary into solving a partial differential equation with initial value. On this basis, according to the equal and scaled principles, the tolerance width of each input is evaluated in an intuitionally geometrical manner, that is, searching the maximum geometry corresponding to the principle inside the exact input error boundary. Finally, two planar parallel mechanisms with different degrees of freedom are introduced as numerical examples to demonstrate the execution and effectiveness of the proposed method.

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