scholarly journals Fault-Tolerant quantum computation with constant overhead

2014 ◽  
Vol 14 (15&16) ◽  
pp. 1339-1371
Author(s):  
Daniel Gottesman
Keyword(s):  
Fault Tolerant ◽  
Quantum Circuit ◽  
Error Correcting Codes ◽  
Parity Check ◽  
Low Density Parity Check ◽  
The Family ◽  
Minimum Number ◽  
Logical Qubits ◽  
Quantum Error ◽  
Parity Check Codes

What is the minimum number of extra qubits needed to perform a large fault-tolerant quantum circuit? Working in a common model of fault-tolerance, I show that in the asymptotic limit of large circuits, the ratio of physical qubits to logical qubits can be a constant. The construction makes use of quantum low-density parity check codes, and the asymptotic overhead of the protocol is equal to that of the family of quantum error-correcting codes underlying the fault-tolerant protocol.

scholarly journals Flag fault-tolerant error correction with arbitrary distance codes

Quantum ◽  
2018 ◽  
Vol 2 ◽  
pp. 53 ◽  
Author(s):  
Christopher Chamberland ◽  
Michael E. Beverland
Keyword(s):  
Error Correction ◽  
Fault Tolerant ◽  
Quantum Error Correction ◽  
Quantum Codes ◽  
Parity Check ◽  
Code Length ◽  
Stabilizer Codes ◽  
Low Density Parity Check ◽  
Quantum Error ◽  
First Time

In this paper we introduce a general fault-tolerant quantum error correction protocol using flag circuits for measuring stabilizers of arbitrary distance codes. In addition to extending flag error correction beyond distance-three codes for the first time, our protocol also applies to a broader class of distance-three codes than was previously known. Flag circuits use extra ancilla qubits to signal when errors resulting fromvfaults in the circuit have weight greater thanv. The flag error correction protocol is applicable to stabilizer codes of arbitrary distance which satisfy a set of conditions and uses fewer qubits than other schemes such as Shor, Steane and Knill error correction. We give examples of infinite code families which satisfy these conditions and analyze the behaviour of distance-three and -five examples numerically. Requiring fewer resources than Shor error correction, flag error correction could potentially be used in low-overhead fault-tolerant error correction protocols using low density parity check quantum codes of large code length.

scholarly journals Online scheduled execution of quantum circuits protected by surface codes

2017 ◽  
Vol 17 (15&16) ◽  
pp. 1335-1348 ◽  
Author(s):  
Alexandru Paler ◽  
Austin G. Fowler ◽  
Robert Wille
Keyword(s):  
Quantum Information Processing ◽  
Fault Tolerant ◽  
Dynamic Structure ◽  
Quantum Circuit ◽  
Error Correcting Codes ◽  
Quantum Circuits ◽  
Static Scheduling ◽  
Surface Code ◽  
High Level ◽  
Quantum Error

Quantum circuits are the preferred formalism for expressing quantum information processing tasks. Quantum circuit design automation methods mostly use a waterfall approach and consider that high level circuit descriptions are hardware agnostic. This assumption has lead to a static circuit perspective: the number of quantum bits and quantum gates is determined before circuit execution and everything is considered reliable with zero probability of failure. Many different schemes for achieving reliable fault-tolerant quantum computation exist, with different schemes suitable for different architectures. A number of large experimental groups are developing architectures well suited to being protected by surface quantum error correcting codes. Such circuits could include unreliable logical elements, such as state distillation, whose failure can be determined only after their actual execution. Therefore, practical logical circuits, as envisaged by many groups, are likely to have a dynamic structure. This requires an online scheduling of their execution: one knows for sure what needs to be executed only after previous elements have finished executing. This work shows that scheduling shares similarities with place and route methods. The work also introduces the first online schedulers of quantum circuits protected by surface codes. The work also highlights scheduling efficiency by comparing the new methods with state of the art static scheduling of surface code protected fault-tolerant circuits.

New rapid algorithm for detecting girth of low-density Parity-check codes

2013 ◽  
Vol 32 (11) ◽  
pp. 3100-3101
Author(s):  
Jiong-cheng LI ◽  
Gui-yu LI ◽  
Heng-hui XIAO ◽  
Hai-yi HUANG
Keyword(s):  
Low Density ◽  
Parity Check ◽  
Low Density Parity Check ◽  
Parity Check Codes
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