e-beam sustained low power budget air plasmas

2002 ◽  
Author(s):  
P. Palm ◽  
E. Plonjes ◽  
I. Adamovich ◽  
J. Rich
Keyword(s):  
Low Power ◽  
Power Budget ◽  
Air Plasmas

Energy harvesting from quasi-static deformations via bilaterally constrained strips

2018 ◽  
Vol 29 (18) ◽  
pp. 3572-3581
Author(s):  
Suihan Liu ◽  
Ali Imani Azad ◽  
Rigoberto Burgueño
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Mechanical Energy ◽  
Electrical Power ◽  
Energy Resource ◽  
Electrical Energy ◽  
Piezoelectric Energy Harvesting ◽  
Power Budget ◽  
Piezoelectric Energy ◽  
Static Conditions

Piezoelectric energy harvesting from ambient vibrations is well studied, but harvesting from quasi-static responses is not yet fully explored. The lack of attention is because quasi-static actions are much slower than the resonance frequency of piezoelectric oscillators to achieve optimal outputs; however, they can be a common mechanical energy resource: from large civil structure deformations to biomechanical motions. The recent advances in bio-micro-electro-mechanical systems and wireless sensor technologies are motivating the study of piezoelectric energy harvesting from quasi-static conditions for low-power budget devices. This article presents a new approach of using quasi-static deformations to generate electrical power through an axially compressed bilaterally constrained strip with an attached piezoelectric layer. A theoretical model was developed to predict the strain distribution of the strip’s buckled configuration for calculating the electrical energy generation. Results from an experimental investigation and finite element simulations are in good agreement with the theoretical study. Test results from a prototyped device showed that a peak output power of 1.33 μW/cm2 was generated, which can adequately provide power supply for low-power budget devices. And a parametric study was also conducted to provide design guidance on selecting the dimensions of a device based on the external embedding structure.

Low Power Considerations in Ubiquitous Computing

2010 ◽  
pp. 158-174
Author(s):  
Robert Tesch ◽  
Ashok Kumar ◽  
Jamie Mason ◽  
Dania Alvarez ◽  
Mario Di’Mattia ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ubiquitous Computing ◽  
Reducing Power ◽  
Low Power Design ◽  
Power Budget ◽  
Computing Systems ◽  
Research Directions ◽  
Design Considerations ◽  
Battery Technology

Majority of the devices that are used in ubiquitous computing are expected to be as small as possible, be able to perform as many computations as possible, and transmit the results to another device or computer. Such expectations in performance put a pressure on the power budget of such devices. It is a well-known fact that the advances in battery technology are much slower and cannot keep up with the performance demands of tiny gadgets unless new methods of designing and managing hardware and software are developed and used. This chapter will introduce the motivation for low power design considerations by discussing the power limitations of ubiquitous computing devices. Then the chapter will discuss the research directions that are being pursued in literature for reducing power consumption and increasing efficiency of ubiquitous computing systems.

State-of-the-Art Master Slave Flip-Flop Designs for Low Power VLSI Systems

2016 ◽  
pp. 166-198
Author(s):  
Kunwar Singh ◽  
Satish Chandra Tiwari ◽  
Maneesha Gupta
Keyword(s):  
Low Power ◽  
State Of The Art ◽  
Relative Power ◽  
Power Budget ◽  
Comprehensive Overview ◽  
Feedback Strategy ◽  
Flip Flop ◽  
Simulation Results

This chapter presents a comprehensive overview of the conventional fully static master slave flip-flops used in low power VLSI systems where power budget is critical. In addition, the chapter also presents alternative realization of fully static master-slave flip-flops utilizing a modified feedback strategy. The flip-flops designed on the basis of modified architecture have been explained in detail and compared with state-of-the-art master slave flip-flop designs available in the literature. Extensive capacitance calculations have been performed in terms of clock load and capacitance at internal nodes has also been estimated for all the flip-flop configurations. This is executed in order to compare their relative power and delay characteristics which are well supported by simulation results.

scholarly journals Energy and Spectrally Efficient Modulation Scheme for IoT Applications

Sensors ◽  
2018 ◽  
Vol 18 (12) ◽  
pp. 4382 ◽  
Author(s):  
Hany Hussein ◽  
Mohamed Elsayed ◽  
Mahmoud Fakhry ◽  
Usama Sayed Mohamed
Keyword(s):  
Low Power ◽  
Closed Form ◽  
Fading Channels ◽  
Low Cost ◽  
Superior Performance ◽  
Closed Form Expression ◽  
Modulation Scheme ◽  
Power Budget ◽  
Iot Applications ◽  
Phy Layer

Due to the Internet of Things (IoT) requirements for a high-density network with low-cost and low-power physical (PHY) layer design, the low-power budget transceiver systems have drawn momentous attention lately owing to their superior performance enhancement in both energy efficiency and hardware complexity reduction. As the power budget of the classical transceivers is envisioned by using inefficient linear power amplifiers (PAs) at the transmitter (TX) side and by applying high-resolution analog to digital converters (ADCs) at the receiver (RX) side, the transceiver architectures with low-cost PHY layer design (i.e., nonlinear PA at the TX and one-bit ADC at the RX) are mandated to cope with the vast IoT applications. Therefore, in this paper, we propose the orthogonal shaping pulses minimum shift keying (OSP-MSK) as a multiple-input multiple-output (MIMO) modulation/demodulation scheme in order to design the low-cost transceiver architectures associated with the IoT devices. The OSP-MSK fulfills a low-power budget by using constant envelope modulation (CEM) techniques at the TX side, and by applying a low-resolution one-bit ADC at the RX side. Furthermore, the OSP-MSK provides a higher spectral efficiency compared to the recently introduced MIMO-CEM with the one-bit ADC. In this context, the orthogonality between the in-phase and quadrature-phase components of the OSP are exploited to increase the number of transmitted bits per symbol (bps) without the need for extra bandwidth. The performance of the proposed scheme is investigated analytically and via Monte Carlo simulations. For the mathematical analysis, we derive closed-form expressions for assessing the average bit error rate (ABER) performance of the OSP-MSK modulation in conjunction with Rayleigh and Nakagami-m fading channels. Moreover, a closed-form expression for evaluating the power spectral density (PSD) of the proposed scheme is obtained as well. The simulation results corroborate the potency of the conducted analysis by revealing a high consistency with the obtained analytical formulas.

Analysis of the power budget and stability of high-pressure nonequilibrium air plasmas

2000 ◽  
Author(s):  
Igor Adamovich ◽  
J. Rich ◽  
Andrey Chernukho ◽  
Serguei Zhdanok
Keyword(s):  
High Pressure ◽  
Power Budget ◽  
Air Plasmas

Strong rotating flow in stationary droplets in low power budget using wire electrode configuration

2019 ◽  
Vol 40 (22) ◽  
pp. 2971-2978 ◽  
Author(s):  
Golak Kunti ◽  
Anandaroop Bhattacharya ◽  
Suman Chakraborty
Keyword(s):  
Low Power ◽  
Electrode Configuration ◽  
Rotating Flow ◽  
Wire Electrode ◽  
Power Budget

scholarly journals Power Constrained Design Optimization of Analog Circuits Based on Physical gm/ID Characteristics

2007 ◽  
Vol 2 (1) ◽  
pp. 22-28
Author(s):  
Alessandro Girardi ◽  
Sergio Bampi
Keyword(s):  
Low Power ◽  
Design Optimization ◽  
Analog Circuits ◽  
Compact Model ◽  
Power Budget ◽  
Analytic Expressions ◽  
Low Power Cmos ◽  
Optimization Methodology ◽  
Moderate Inversion ◽  
Optimization Loop

This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimization guide. Our custom layout tool LIT implements and uses the ACM MOS compact model in the optimization loop. The methodology is implemented for automation within LIT and exploits all design space through the simulated annealing optimization process, providing solutions close to optimum with a single technology-dependent curve and accurate expressions for transconductance and current valid in all operation regions. The compact model itself contributes to convergence and to optimized implementations, since it has analytic expressions which are continuous in all current regimes, including weak and moderate inversion. The advantage of constraining the optimization within a power budget is of great importance for low-power CMOS. As examples we show the optimization results obtained with LIT, resulting in significant power savings, for the design of a folded-cascode and a two-stage Miller operational amplifier.

Thermally Reliable Ultra-Low-Power Voltage Reference to Regulator Converter

2020 ◽  
pp. 2150024
Author(s):  
George M. Joseph ◽  
Emmanouel George ◽  
Prathyush S. Pramod ◽  
Zameel Nizam ◽  
S. Krishnapriya ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Current Efficiency ◽  
Power Supply ◽  
Cmos Technology ◽  
Surveillance Systems ◽  
Voltage Reference ◽  
Power Budget ◽  
Line Load ◽  
Ultra Low Power

A regulated power supply with ultra-low-power consumption, high current efficiency, line, load and thermal stability is an essential part of any high precision electronic system with stringent power budget such as biomedical sensors or military surveillance systems. In this paper, we propose an ultra-low-power, MOSFET only, voltage reference to regulator convertor, proficient to work below 1 V with reduced power consumption. The proposed idea incorporates the provision to integrate any voltage reference module to a comparator-based circuit so as to transform it to a voltage regulator having similar temperature coefficient (TC) and line regulation as that of the interfaced voltage reference. It is also able to produce a reliable output accounting to load fluctuations. The circuit is simulated in 0.18[Formula: see text][Formula: see text]m CMOS technology using Cadence Virtuoso simulation suit. The complete circuit was found to draw a quiescent current of 319.9 pA with a notable current efficiency of 99.99997% at 27∘C on driving a load of 1[Formula: see text]mA along with a Power Supply Rejection Ratio (PSRR) of [Formula: see text][Formula: see text]dB additional to that of the reference. The proposed circuit will occupy an area of 0.00064[Formula: see text]mm2 and offer a TC as low as 1.7077 ppm/∘C. The whole MOS approach facilitates a reduction in die area and process simplicity.

scholarly journals An 868 MHz 7.5 µW wake-up receiver with −60 dBm sensitivity

2016 ◽  
Vol 5 (2) ◽  
pp. 433-446 ◽  
Author(s):  
Sadok Bdiri ◽  
Faouzi Derbel ◽  
Olfa Kanoun
Keyword(s):  
Low Power ◽  
Real Time ◽  
Sensor Nodes ◽  
Time Behavior ◽  
Active Components ◽  
Power Budget ◽  
Sleep State ◽  
Typical Application ◽  
Ultra Low Power ◽  
Idle Listening

Abstract. In wireless sensor networks (WSNs), batteries are unlikely to be replaced or recharged once they get depleted, because of costs and feasibility. In a typical application, sensor nodes should be accessible and able to respond within a defined period of time, especially in real-time applications. However, the idle listening of the radio wastes most of the energy since the radio transceiver is constantly active. On the other hand, putting it into sleep state disconnects the node from the network. To cope with such a challenge, an ultra-low-power radio receiver referred to as a wake-up receiver (WuRx) handles the idle listening while keeping the main radio completely off. A WuRx consumes much less power than the main transceiver and triggers an interrupt only when a packet with a user-defined address is received. Embedding such a device enables better event-triggered applications where real-time behavior is required and a longer lifetime is mandatory. The proposed WuRx features practical sensitivity and includes the minimum number of active components in order to remain within the power budget. In this paper, an ultra-low-power WuRx with a power of 7.5 µW and a sensitivity of −60 dBm is developed. The decoding process of 16 bit of a wake-up packet (WuPt) takes less than 15 ms.

Sign in / Sign up

Export Citation Format

Share Document