Flight Control System Architecture Optimization for Fly-By-Wire Airliners

2007 ◽  
Vol 30 (4) ◽  
pp. 1023-1029 ◽  
Author(s):  
Christophe Bauer ◽  
Kristen Lagadec ◽  
Christian Bès ◽  
Marcel Mongeau
Keyword(s):  
Control System ◽  
Flight Control ◽  
System Architecture ◽  
Flight Control System ◽  
Control System Architecture ◽  
Architecture Optimization

scholarly journals Environmental and Flight Control System Architecture Optimization from a Family Concept Design Perspective

2020 ◽  
Author(s):  
Carlos Cabaleiro de la Hoz ◽  
Jasper H. Bussemaker ◽  
Marco Fioriti ◽  
Luca Boggero ◽  
Pier Davide Ciampa ◽  
...  
Keyword(s):  
Control System ◽  
Flight Control ◽  
System Architecture ◽  
Concept Design ◽  
Flight Control System ◽  
Design Perspective ◽  
Control System Architecture ◽  
Architecture Optimization

scholarly journals Reliable flight control system architecture for agile airborne platforms: an asymmetric multiprocessing approach

2019 ◽  
Vol 123 (1264) ◽  
pp. 840-862 ◽  
Author(s):  
Shibarchi Majumder ◽  
Jens Frederik Dalsgaard Nielsen ◽  
Thomas Bak ◽  
Anders la Cour-Harbo
Keyword(s):  
Control System ◽  
Flight Control ◽  
Unmanned Aircraft ◽  
Flight Control System ◽  
Fpga Chip ◽  
Distributed Implementation ◽  
Aircraft System ◽  
On Chip ◽  
Control System Architecture ◽  
Critical Subsystems

AbstractSystem software subsystems in an unmanned aircraft system share hardware resources due to space, weight, and power constraints. Such subsystems have different criticality, requirements, and failure rates, and can cause undesired interference when sharing the same hardware. A component with high failure rate can reduce the reliability of the system unless a fault containment mechanism is adopted.This work proposes an asymmetric multiprocessor architecture to establish isolation at the hardware level for distributed implementation of safety-critical subsystems along with user defined payload subsystems on the same hardware with minimally reduced reliability of the system. To achieve that, subsystems are strategically segregated in separate processors, connected to an on-chip protective interconnect for inter-processor communications. A custom watchdog and reset mechanism are implemented to reset a specific processor without affecting the entire system if required. The architecture is demonstrated on a FPGA chip. In addition, an example of an optimised distribution is provided for a specific flight control system with five subsystems.

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