scholarly journals Development of a high-speed rail transmission system using digital signal processors for railway signalling

2008 ◽  
Author(s):  
H. Mochizuki ◽  
S. Takahashi ◽  
H. Nakamura ◽  
S. Nishida ◽  
R. Ishikawa
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Transmission System ◽  
Digital Signal Processors ◽  
High Speed Rail ◽  
Railway Signalling ◽  
Signal Processors

Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

2021 ◽  
Vol 9 (9) ◽  
pp. 66-70
Author(s):  
Nakul C. Kubsad
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Digital Signal ◽  
Full Adder ◽  
Digital Signal Processors ◽  
Transmission Gate ◽  
Logical Operations ◽  
Recent Advancement ◽  
Voltage Swing ◽  
Signal Processors

Abstract: Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.

High Speed Vedic Multiplier for Digital Signal Processors

2009 ◽  
Vol 55 (6) ◽  
pp. 282 ◽  
Author(s):  
Ramesh Pushpangadan ◽  
Vineeth Sukumaran ◽  
Rino Innocent ◽  
Dinesh Sasikumar ◽  
Vaisak Sundar
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Vedic Multiplier ◽  
Signal Processors

scholarly journals Enhanced and Efficient Carry Select Adder with Minimal Delay

2021 ◽  
Author(s):  
G. Srividhya ◽  
T. Sivasakthi ◽  
R. Srivarshini ◽  
P. Varshaa ◽  
S. Vijayalakshmi
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Digital Signal Processors ◽  
Digital World ◽  
Carry Select Adder ◽  
Image Processors ◽  
Improved Model ◽  
Signal Processors

In today’s digital world, Arithmetic computations have been evolved as a core factor in digital signal processors, micro-controllers, and systems using arithmetic and logical operations such as adders, multipliers, image processors, and signal processors. One of the elements that play an important role in performing arithmetic calculations is an adder. Among many adders, the Carry Select Adder produces less propagation delay. However, there may be an increased delay, power consumption, and area required in the case of a normal Carry Select Adder. To overcome the mentioned drawbacks, an improved model of Carry Select Adder has been designed that uses Binary to Excess – 1 Converter. Instead of using multiple blocks of Ripple Carry Adders (RCAs), it is efficient and effective if one of the blocks is replaced with Binary to Excess – 1 Converter. As a result, we can achieve a high speed adder with minimal delay, minimal power, and reduced area.

scholarly journals FPGA Based Vector Control of Induction Motor

2020 ◽  
Vol 9 (4) ◽  
pp. 572-577
Keyword(s):  
Induction Motor ◽  
High Speed ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Electronic Industry ◽  
New Approach ◽  
The Past ◽  
Field Programmable ◽  
Signal Processors ◽  
Very High

To get the desired response of the sensor less Vector controlled Induction Motor (SVC-IM) by the experimental setup, the controller implementation for the generation of the PWM signals is the key role. It is possible with the rapid growth of electronic industry such as high speed digital signal processors (DSPs) with micro controllers available in the present market. In the past DSP technologies were used to realize the several SVC-IM schemes, i.e. KF, PI, GA and PSO respectively. However, it creates issues related to the time delay and execution of the PWM signals, etc., as a results system becomes complex. Therefore a new approach is implemented to overcome the issues related to the execution time, namely Field Programmable Gate Array (FPGA) processors are suggested in the present market. Moreover the programming is done using very high speed hardware descriptive language (VHDL)

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