Measurement of Voltages due to Electrostatic Discharge in a Storage Tank during the Pneumatic Conveyance of Powders

Abstract This paper outlines the systematic isolation of an electrostatic discharge defect on a depletion-mode FET. Topics covered are fault isolation, FIB-STEM cross-section and EDS analysis, and defect simulation. Multiple GaAs PA devices were submitted for analysis after failing different reliability stresses. Fault isolation revealed ESD damage on a DFET connected to the VMODE0 pin. Simulation of the failure showed that, most likely, the defect was caused by CDM stress. A design change of inserting a resistor between the VMODE0 pin and the DFET made the device more robust against CDM stress.

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A Methodology for Characterizing System-Level ESD Sensitivity

ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2004p0277 ◽

2004 ◽

Author(s):

Marie-Pascale Chagny ◽

John A. Naoum

Keyword(s):

Electrostatic Discharge ◽

Computer Systems ◽

Electronic Equipment ◽

Experimental Methodology ◽

Computer Users ◽

System Level ◽

Permanent Damage ◽

Design Improvement ◽

Desktop Computers

Abstract Over the years, failures induced by an electrostatic discharge (ESD) have become a major concern for semiconductor manufacturers and electronic equipment makers. The ESD events that cause destructive failures have been studied extensively [1, 2]. However, not all ESD events cause permanent damage. Some events lead to recoverable failures that disrupt system functionality only temporarily (e.g. reboot, lockup, and loss of data). These recoverable failures are not as well understood as the ones causing permanent damage and tend to be ignored in the ESD literature [3, 4]. This paper analyzes and characterizes how these recoverable failures affect computer systems. An experimental methodology is developed to characterize the sensitivity of motherboards to ESD by simulating the systemlevel ESD events induced by computer users. The manuscript presents a case study where this methodology was used to evaluate the robustness of desktop computers to ESD. The method helped isolate several weak nets contributing to the failures and identified a design improvement. The result was that the robustness of the systems improved by a factor of 2.

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Characterization of CMOS Structures (0.6 µm process) Submitted to HBM and COM ESD Stress Tests

ISTFA 1997: Conference Proceedings from the 23rd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa1997p0315 ◽

1997 ◽

Author(s):

G. Meneghesso ◽

E. Zanoni ◽

P. Colombo ◽

M. Brambilla ◽

R. Annunziata ◽

...

Keyword(s):

Electron Microscopy ◽

Electrostatic Discharge ◽

Stress Test ◽

Complete Characterization ◽

Stress Tests ◽

Test Procedures ◽

Emission Microscopy ◽

Fast Rise ◽

Scanning Electron

Abstract In this work, we present new results concerning electrostatic discharge (ESD) robustness of 0.6 μm CMOS structures. Devices have been tested according to both HBM and socketed CDM (sCDM) ESD test procedures. Test structures have been submitted to a complete characterization consisting in: 1) measurement of the tum-on time of the protection structures submitted to pulses with very fast rise times; 2) ESD stress test with the HBM and sCDM models; 3) failure analysis based on emission microscopy (EMMI) and Scanning Electron Microscopy (SEM).

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