scholarly journals Ground Leakage Current Caused by Common-Mode Voltage of PWM inverter

2020 ◽  
Vol 1 (1) ◽  
pp. 15-25
Author(s):  
Jerzy Ryszard Szymański ◽  
Marta Żurek-Mortka
Keyword(s):  
Pulse Width Modulation ◽  
Differential Mode ◽  
Common Mode ◽  
Current Form ◽  
Pwm Inverter ◽  
Common Mode Voltage ◽  
Three Phase ◽  
Voltage Phase ◽  
Shock Protection ◽  
Parasitic Currents

In railway tractive vehicles, three-phase PWM (Pulse Width Modulation) inverters generate parasitic Differential-Mode Voltages (DMV) and Common-Mode Voltages (CMV). Parasitic voltages are a side effect of using the width modulation to shape the phase-to-phase inverter’s voltage. In this article, the authors present a mathematical description of the DM and CM voltages and carry out their spectral analysis. Based on the spectral harmonics analysis, the authors present a method for filtration of harmonics of DM and CM voltages aimed at limiting the capacitance parasitic currents: due to DM voltage – phase-to-phase parasitic current and CM voltage – ground parasitic currents. As the final result of the tests, almost complete elimination of leakage parasitic current form PE shock protection system was achieved.

scholarly journals Opposite Triangle Carrier with SVPWM for Common-Mode Voltage Reduction in Dual Three Phase Motor Drives

Energies ◽  
2021 ◽  
Vol 14 (2) ◽  
pp. 282
Author(s):  
Seon-Ik Hwang ◽  
Jang-Mok Kim
Keyword(s):  
Electromagnetic Interference ◽  
Pulse Width Modulation ◽  
Motor Drives ◽  
Common Mode ◽  
Pwm Inverter ◽  
Common Mode Voltage ◽  
Voltage Vector ◽  
Three Phase ◽  
The Common ◽  
Zero Voltage

The common-mode voltage (CMV) generated by the switching operation of the pulse width modulation (PWM) inverter leads to bearing failure and electromagnetic interference (EMI) noises. To reduce the CMV, it is necessary to reduce the magnitude of dv/dt and change the frequency of the CMV. In this paper, the range of the CMV is reduced by using opposite triangle carrier for ABC and XYZ winding group, and the change in frequency in the CMV is reduced by equalizing the dwell time of the zero voltage vector on ABC and XYZ winding group of dual three phase motor.

scholarly journals SVPWM Method for Multilevel Indirect Matrix Converter with Eliminate Common Mode Voltage

2019 ◽  
Vol 9 (7) ◽  
pp. 1342
Author(s):  
Nguyen Dinh Tuyen ◽  
Le Minh Phuong
Keyword(s):  
Pulse Width Modulation ◽  
Experimental System ◽  
Power Converter ◽  
Matrix Converter ◽  
Modulation Method ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Three Phase ◽  
Sinusoidal Input ◽  
Bidirectional Power Flow

The multilevel indirect matrix converter (IMC) is a merit of power converter for feeding a three-phase load from three-phase power supply because it has several attractive features such as: Sinusoidal input/output currents, bidirectional power flow, long lifetime due to the absence of bulky electrolytic capacitors. As compared to the conventional IMC, the multilevel IMC provides high output performance by increasing the level of output voltage. In this paper, the novel approach topology of multilevel IMC by using the combination of the cascaded rectifier and the three-level T-Type inverter is introduced. Furthermore, the new space vector pulse width modulation (SVPWM) method for the presented multilevel IMC that eliminate the common-mode voltage is proposed in this paper. The simulation study is carried out in PSIM software to verify the proposed modulation method. Then, an experimental system is built using a three-phase RL load, a multilevel IMC, a DSP controller board and other elements to verify the effectiveness of the proposed modulation method. Some simulation and experimental results are illustrated to confirm the theory analysis.

scholarly journals Common-Mode Reduction SVPWM for Three-Phase Motor Fed by Two-Level Voltage Source Inverter

Energies ◽  
2020 ◽  
Vol 13 (15) ◽  
pp. 3884
Author(s):  
Jian Zheng ◽  
Mingcheng Lyu ◽  
Shengqing Li ◽  
Qiwu Luo ◽  
Keyuan Huang
Keyword(s):  
High Frequency ◽  
Pulse Width ◽  
Pulse Width Modulation ◽  
Voltage Source ◽  
Switching Frequency ◽  
Voltage Source Inverter ◽  
Large Magnitude ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Three Phase

Aiming at the problem of large magnitude and high frequency of common-mode voltage (CMV) when space vector pulse width modulation (SVPWM) is used in a three-phase motor fed by a two-level voltage source inverter, a common-mode reduction SVPWM (CMRSVPWM) is studied. In this method, six new sectors are obtained by rotating six sectors of conventional SVPWM by 30°. In odd-numbered sectors, only three non-zero vectors with odd subscripts are used for synthesis, while in even-numbered sectors, only three non-zero vectors with even subscripts are used for synthesis. The actuation durations of three non-zero vectors in each switching period in each sector are given. Simulation and experimental results show that, compared with the conventional SVPWM, the CMV magnitude of CMRSVPWM is reduced by 66.67% and the CMV frequency of CMRSVPWM is reduced from the original switching frequency to the triple fundamental frequency. At the same time, the current, torque and speed of the motor are still good.

scholarly journals A Method for the Simultaneous Suppression of DC Capacitor Fluctuations and Common-Mode Voltage in a Five-Level NPC/H Bridge Inverter

Energies ◽  
2019 ◽  
Vol 12 (5) ◽  
pp. 779 ◽  
Author(s):  
Ming Wu ◽  
Zhenhao Song ◽  
Zhipeng Lv ◽  
Kai Zhou ◽  
Qi Cui
Keyword(s):  
Pulse Width Modulation ◽  
Neutral Point ◽  
Common Mode ◽  
Mapping Algorithm ◽  
Common Mode Voltage ◽  
Point Potential ◽  
Voltage Vector ◽  
Three Phase ◽  
Simulation And Experiment ◽  
The Common

To suppress the direct current (DC) capacitor voltage fluctuations and the common-mode voltage (CMV) in a three-phase, five-level, neutral-point-clamped (NPC)/H-bridge inverter, this paper analyzes the influence of all voltage vectors on the neutral point potential of each phase under different pulse mappings in detail with an explanation of the CMV distribution. Then, based on the traditional space vector pulse width modulation (SVPWM) algorithm, a dual-pulse-mapping algorithm is proposed to suppress the DC capacitor fluctuations and the CMV simultaneously. In the algorithm, the reference voltage synthesis selects the voltage vector that has the smallest CMV value as the priority. In addition, the two kinds of pulse mappings that have opposite effects on the neutral point potential are switched to output. At the same time, regulating factors are introduced to adjust the working time of each voltage vector under the two pulse mappings; then, the capacitor voltages can be balanced. Both the simulation and experiment demonstrate the algorithm’s effectiveness.

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