scholarly journals Analysis and Optimization of the Sizes of the Iteration Space Tiles During the Parallelization of Program Loop Operators

2018 ◽  
Vol 3 (1) ◽  
pp. 1-6 ◽  
Author(s):  
Alexander Chemeris ◽  
◽  
Sergii Sushko
Keyword(s):  
2020 ◽  
Vol 4 (OOPSLA) ◽  
pp. 1-30 ◽  
Author(s):  
Ryan Senanayake ◽  
Changwan Hong ◽  
Ziheng Wang ◽  
Amalee Wilson ◽  
Stephen Chou ◽  
...  

Author(s):  
Aniket Shivam ◽  
Alexandru Nicolau ◽  
Alexander V. Veidenbaum ◽  
Mario Mango Furnari ◽  
Rosario Cammarota

1996 ◽  
Vol 06 (01) ◽  
pp. 173-184 ◽  
Author(s):  
WESLEY K. KAPLOW ◽  
BOLESLAW K. SZYMANSKI

We present a novel, compile-time method for determining the cache performance of the loop nests in a program. The cache hit-rates are produced by applying the reference string, determined during compilation, to an architecturally parameterized cache simulator. We also describe a heuristic that uses this method for compile-time optimization of loop ranges in iteration-space blocking. The results of the loop program optimizations are presented for different parallel program benchmarks and various processor architectures, such as IBM SP1 RS/6000, the SuperSPARC, and the Intel 1860.


Author(s):  
Arun Kejariwal ◽  
Alexandru Nicolau ◽  
Utpal Banerjee ◽  
Alexander V. Veidenbaum ◽  
Constantine D. Polychronopoulos

2001 ◽  
Vol 50 (12) ◽  
pp. 1321-1335 ◽  
Author(s):  
M. Kandemir ◽  
J. Ramanujam ◽  
A. Choudhary ◽  
P. Banerjee

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