A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices

Background: Output polarity of the sub-function is generally considered to reduce the area and power of a circuit at the two-level realization. Along with area and power, the power-density is also one of the significant parameter which needs to be consider, because power-density directly converges to circuit temperature. More than 50% of the modern day integrated circuits are damaged due to excessive overheating. Methods: This work demonstrates the impact of efficient power density based logic synthesis (in the form of suitable polarity selection of sub-function of Programmable Logic Arrays (PLAs) for its multilevel realization) for the reduction of temperature. Two-level PLA optimization using output polarity selection is considered first and compared with other existing techniques and then And-Invert Graphs (AIG) based multi-level realization has been considered to overcome the redundant solution generated in two-level synthesis. AIG nodes and associated power dissipation can be reduced by rewriting, refactoring and balancing technique. Reduction of nodes leads to the reduction of the area but on the contrary increases power and power density of the circuit. A meta-heuristic search approach i.e., Nondominated Sorting Genetic Algorithm-II (NSGA-II) is proposed to select the suitable output polarity of PLA sub-functions for its optimal realization. Results: Best power density based solution saves up to 8.29% power density compared to ‘espresso – dopo’ based solutions. Around 9.57% saving in area and 9.67% saving in power (switching activity) are obtained with respect to ‘espresso’ based solution using NSGA-II. Conclusion: Suitable output polarity realized circuit is converted into multi-level AIG structure and synthesized to overcome the redundant solution at the two-level circuit. It is observed that with the increase in power density, the temperature of a particular circuit is also increases.

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Multi-level approximate logic synthesis under general error constraints

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) ◽

10.1109/iccad.2014.7001398 ◽

2014 ◽

Cited By ~ 29

Author(s):

Jin Miao ◽

Andreas Gerstlauer ◽

Michael Orshansky

Keyword(s):

Logic Synthesis ◽

Multi Level ◽

General Error

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Continuous window functions for NFFT

Advances in Computational Mathematics ◽

10.1007/s10444-021-09873-8 ◽

2021 ◽

Vol 47 (4) ◽

Author(s):

Daniel Potts ◽

Manfred Tasche

Keyword(s):

Fourier Transform ◽

Shape Parameter ◽

Optimal Choice ◽

Approximate Algorithm ◽

Window Function ◽

Truncation Parameter ◽

Error Constant ◽

Window Functions ◽

Nonequispaced Fast Fourier Transform ◽

Error Behavior

AbstractIn this paper, we study the error behavior of the nonequispaced fast Fourier transform (NFFT). This approximate algorithm is mainly based on the convenient choice of a compactly supported window function. Here, we consider the continuous Kaiser–Bessel, continuous exp-type, sinh-type, and continuous cosh-type window functions with the same support and same shape parameter. We present novel explicit error estimates for NFFT with such a window function and derive rules for the optimal choice of the parameters involved in NFFT. The error constant of a window function depends mainly on the oversampling factor and the truncation parameter. For the considered continuous window functions, the error constants have an exponential decay with respect to the truncation parameter.

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The Fusion of Secure Function Evaluation and Logic Synthesis

IEEE Security & Privacy ◽

10.1109/msec.2020.3049062 ◽

2021 ◽

pp. 0-0

Author(s):

Siam U. Hussain ◽

M. Sadegh Riazi ◽

Farinaz Koushanfar

Keyword(s):

Logic Synthesis ◽

Function Evaluation ◽

Secure Function Evaluation

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