High-level synthesis of software-customizable floating-point cores

2018 ◽  
Author(s):  
Samridhi Bansal ◽  
Hsuan Hsiao ◽  
Tomasz Czajkowski ◽  
Jason H. Anderson
Keyword(s):  
High Level Synthesis ◽  
Floating Point ◽  
High Level

Area Optimization of Combined Integer and Floating Point Circuits in High-Level Synthesis

2008 ◽  
Author(s):  
Esther Andres ◽  
Maria C. Molina ◽  
Guillermo Botella ◽  
Alberto del Barrio ◽  
Jose M. Mendias
Keyword(s):  
High Level Synthesis ◽  
Floating Point ◽  
Area Optimization ◽  
High Level

scholarly journals High-Level Synthesis under Fixed-Point Accuracy Constraint

2012 ◽  
Vol 2012 ◽  
pp. 1-14 ◽  
Author(s):  
Daniel Menard ◽  
Nicolas Herve ◽  
Olivier Sentieys ◽  
Hai-Nam Nguyen
Keyword(s):  
Signal Processing ◽  
Fixed Point ◽  
Word Length ◽  
High Level Synthesis ◽  
Floating Point ◽  
Fixed Point Arithmetic ◽  
Resource Binding ◽  
High Level ◽  
Point Arithmetic ◽  
Length Optimization

Implementing signal processing applications in embedded systems generally requires the use of fixed-point arithmetic. The main problem slowing down the hardware implementation flow is the lack of high-level development tools to target these architectures from algorithmic specification language using floating-point data types. In this paper, a new method to automatically implement a floating-point algorithm into an FPGA or an ASIC using fixed-point arithmetic is proposed. An iterative process on high-level synthesis and data word-length optimization is used to improve both of these dependent processes. Indeed, high-level synthesis requires operator word-length knowledge to correctly execute its allocation, scheduling, and resource binding steps. Moreover, the word-length optimization requires resource binding and scheduling information to correctly group operations. To dramatically reduce the optimization time compared to fixed-point simulation-based methods, the accuracy evaluation is done through an analytical method. Different experiments on signal processing algorithms are presented to show the efficiency of the proposed method. Compared to classical methods, the average architecture area reduction is between 10% and 28%.

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