A fast and effective lookahead and fractional search based scheduling algorithm for high-level synthesis

2018 ◽  
Author(s):  
Shantanu Dutt ◽  
Ouwen Shi
Keyword(s):  
Scheduling Algorithm ◽  
High Level Synthesis ◽  
High Level

Dependency Graph-based High-level Synthesis for Maximum Instruction Parallelism

2021 ◽  
Vol 14 (4) ◽  
pp. 1-15
Author(s):  
Zhenghua Gu ◽  
Wenqing Wan ◽  
Jundong Xie ◽  
Chang Wu
Keyword(s):  
Performance Optimization ◽  
Directed Acyclic Graph ◽  
Scheduling Algorithm ◽  
Dependency Graph ◽  
High Level Synthesis ◽  
Limiting Factor ◽  
Circuit Performance ◽  
State Transition Graph ◽  
High Level ◽  
Basic Blocks

Performance optimization is an important goal for High-level Synthesis (HLS). Existing HLS scheduling algorithms are all based on Control and Data Flow Graph (CDFG) and will schedule basic blocks in sequential order. Our study shows that the sequential scheduling order of basic blocks is a big limiting factor for achievable circuit performance. In this article, we propose a Dependency Graph (DG) with two important properties for scheduling. First, DG is a directed acyclic graph. Thus, no loop breaking heuristic is needed for scheduling. Second, DG can be used to identify the exact instruction parallelism. Our experiment shows that DG can lead to 76% instruction parallelism increase over CDFG. Based on DG, we propose a bottom-up scheduling algorithm to achieve much higher instruction parallelism than existing algorithms. Hierarchical state transition graph with guard conditions is proposed for efficient implementation of such high parallelism scheduling. Our experimental results show that our DG-based HLS algorithm can outperform the CDFG-based LegUp and the state-of-the-art industrial tool Vivado HLS by 2.88× and 1.29× on circuit latency, respectively.

Optimal Design of a VLSI Processor with Spatially and Temporally Parallel Structure

1996 ◽  
Vol 8 (6) ◽  
pp. 516-523
Author(s):  
Michitaka Kameyama ◽  
◽  
Masayuki Sasaki
Keyword(s):  
Delay Time ◽  
Scheduling Algorithm ◽  
High Level Synthesis ◽  
Parallel Structure ◽  
Data Flow Graph ◽  
Silicon Area ◽  
Suitable Combination ◽  
Minimum Delay ◽  
High Level ◽  
Minimum Delay Time

In intelligent integrated systems such as robotics for autonomous work, it is essential to respond to the change of the environment very quickly. Therefore, the development of special-purpose VLSI processors with minimum delay time becomes a very important subject. A suitable combination of spatially parallel and temporally parallel processing is very important to realize the minimum delay time. In this article, we present a scheduling algorithm for high-level synthesis, where the input to the scheduler is a behavioral description viewed as a data flow graph. The scheduler minimizes the delay time under the constraint of a silicon area and I/O pins.

scholarly journals A scheduling algorithm for optimization and early planning in high-level synthesis

2005 ◽  
Vol 10 (1) ◽  
pp. 33-57 ◽  
Author(s):  
Seda Ogrenci Memik ◽  
Ryan Kastner ◽  
Elaheh Bozorgzadeh ◽  
Majid Sarrafzadeh
Keyword(s):  
Scheduling Algorithm ◽  
High Level Synthesis ◽  
High Level
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