scholarly journals Parallel overloaded CDMA crossbar for network on chip

2019 ◽  
Vol 32 (1) ◽  
pp. 105-118
Author(s):  
Ashok Kumar ◽  
P. Dananjayan
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Large Network ◽  
Network Systems ◽  
Mesh Topology ◽  
Field Programmable ◽  
On Chip ◽  
Code Division Multiple

For high performance of Network on Chip (NoC), Code Division Multiple Access (CDMA) technique is used recently due to its fixed communication delay, reduced area utilisation and low power consumption. The CDMA system uses Walsh based spreading code which improves the bandwidth efficiency. On the contrary, it is not effective when the number of nodes present in the system increases. Overloaded CDMA (OCDMA) is presented for such large network systems. In this paper, OCDMA crossbar is modified and advanced with parallel encoding and decoding operation using orthogonal gold codes for improving the speed of crossbar thereby obtaining high performance in NoC switch. A modified crossbar consisting of extra processing elements is used to enhance the performance of NoC based System on Chip (SoC) system. This work is simulated on Xilinx tool and implemented in Vertex-6 (XC6VLX760) Field Programmable Gate Array (FPGA) device. The proposed work is implemented for four ports, eight ports and sixteen ports with deterministic X-Y routing algorithm in 3 3 NoC design with mesh topology. This NoC switch shows 9.79% improvement in delay and shows 20.76% improvement in power consumption when compared to the existing CDMA NoCs for 8 bit data packet.

scholarly journals Reducing Total Power Consumption and Total Area Techniques for Network-on-Chip Through Disable Cores and Routers Based on Clustering Method

2018 ◽  
Vol 10 (2) ◽  
pp. 514
Author(s):  
Ng Yen Phing ◽  
M.N. Mohd Warip ◽  
Phaklen Ehkan ◽  
S.Y. Teo
Keyword(s):  
Power Consumption ◽  
Large Scale ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Total Power ◽  
Clustering Method ◽  
Mesh Topology ◽  
Total Power Consumption ◽  
Promising Solution ◽  
On Chip

<span lang="EN-US">Network-on-Chip (NoC) is a promising solution to overcome the communication problem of System-on-Chip (SoC) architecture. The execution of topology, routing algorithm and switching technique is significant because it powerfully affects the overall performance of NoC. In the Network-on-Chip, the total power consumption increasing due to the large scale of network. In order to solve it, a clustering method and disable cores and routers based on clustering method is apply onto mesh based NoC architecture. In the proposed approach, the optimization of total area and total power consumption are the major concern. Experiment results show that the proposed method outperformas the existing work. The clustering-mesh based method reduced the total area by 22% to 40 % and total power consumption by 22% to 56% compare to mesh topology. In addition, the proposed method by disable cores and routers based on clustering-mesh based method has decrease the total area by 45% to 87% and total power consumption by 33% to 75% compare to mesh topology.</span>

Design of Router Supporting Multiply Routing Algorithm for NoC

2014 ◽  
Vol 981 ◽  
pp. 431-434
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Chang Chun Dong ◽  
Lin Hai Cui
Keyword(s):  
Complex System ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Deterministic Routing ◽  
Key Features ◽  
Design Challenge ◽  
On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

Comparative Performance Analysis of 
Selected Routing Algorithms by Load Variation of 2-Dimensional Mesh Topology Based 
Network-On-Chip

2021 ◽  
Vol 20 (3) ◽  
pp. 1-6
Author(s):  
Mohammed Shaba Saliu ◽  
Muyideen Omuya Momoh ◽  
Pascal Uchenna Chinedu ◽  
Wilson Nwankwo ◽  
Aliu Daniel
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Injection Rate ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Comparative Performance ◽  
Traffic Pattern ◽  
Mesh Topology ◽  
Similar Vein ◽  
On Chip

Network-on-Chip (NoC) has been proposed as a viable solution to the communication challenges on System-on-Chips (SoCs). As the communication paradigm of SoC, NoCs performance depends mainly on the type of routing algorithm chosen. In this paper different categories of routing algorithms were compared. These include XY routing, OE turn model adaptive routing, DyAD routing and Age-Aware adaptive routing.  By varying the load at different Packet Injection Rate (PIR) under random traffic pattern, comparison was conducted using a 4 × 4 mesh topology. The Noxim simulator, a cycle accurate systemC based simulator was employed. The packets were modeled as a Poisson distribution; first-in-first-out (FIFO) input buffer channel with a depth of five (5) flits and a flit size of 32 bits; and a packet size of 3 flits respectively. The simulation time was 10,000 cycles. The findings showed that the XY routing algorithm performed better when the PIR is low.  In a similar vein, the DyAD routing and Age-aware algorithms performed better when the load i.e. PIR is high.

scholarly journals Low power network on chip architectures: A survey

2020 ◽  
Vol 2 (3) ◽  
pp. 158-168
Author(s):  
Muhammad Raza Naqvi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Network Architecture ◽  
High Performance ◽  
State Of The Art ◽  
Network On Chip ◽  
System On Chip ◽  
Power Network ◽  
Network Routers ◽  
On Chip

Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

Reducing the number of passing links in the 2D-NoC for performance and reliability improvement

2020 ◽  
Vol 17 (5) ◽  
pp. 621-632
Author(s):  
Seyyed Javad Seyyed Mahdavi Chabok ◽  
Seyed Amin Alavi
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Network Reliability ◽  
Telecommunication Network ◽  
High Reliability ◽  
Routing Algorithm ◽  
Network Size ◽  
Content Type ◽  
Probability Of Collision ◽  
On Chip

Purpose The routing algorithm is one of the most important components in designing a network-on-chip (NoC). An effective routing algorithm can cause better performance and throughput, and thus, have less latency, lower power consumption and high reliability. Considering the high scalability in networks and fault occurrence on links, the more the packet reaches the destination (i.e. to cross the number of fewer links), the less the loss of packets and information would be. Accordingly, the proposed algorithm is based on reducing the number of passed links to reach the destination. Design/methodology/approach This paper presents a high-performance NoC that increases telecommunication network reliability by passing fewer links to destination. A large NoC is divided into small districts with central routers. In such a system, routing in large routes is performed through these central routers district by district. Findings By reducing the number of links, the number of routers also decreases. As a result, the power consumption is reduced, the performance of the NoC is improved, and the probability of collision with a faulty link and network latency is decreased. Originality/value The simulation is performed using the Noxim simulator because of its ability to manage and inject faults. The proposed algorithm, XY routing, as a conventional algorithm for the NoC, was simulated in a 14 × 14 network size, as the typical network size in the recent works.

Network-on-Chip Especially for Video Coding Applications Using Multilayer Mesh Topology

2019 ◽  
Vol 12 (3) ◽  
pp. 247-256
Author(s):  
Kamel Messaoudi ◽  
Salah Toumi ◽  
El-Bay Bourennane
Keyword(s):  
Video Coding ◽  
Communication System ◽  
Data Transfer ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Mesh Topology ◽  
Global Interconnects ◽  
And Performance ◽  
On Chip ◽  
Scalable Communication

Background: Network on chip is proposed as new reusable and scalable communication system for applications with important number of IPs. The NoC architecture characteristics are based on several factors: the implementation strategy of IPs, the power dissipation, the placement of IPs, data transfer time, the requirements of the given application, etc. The N×M Mesh topology combined with the XY routing algorithm are generally chosen in many studies. Hardware IPs proposed in the literature, for various applications as example video encoders, operates at different frequencies and generally implemented according to several strategies and different bus sizes. Connecting these IPs using the same communication system is very difficult. Methods: In this paper, we present a new topology based on multi-layer mesh topology and adapted for video coding applications. The proposed topology exploits the video coding information regarding groups of cores that communicate through two cores only. The idea is to use a specific NoC for each group of cores and connect the NoCs with bridge in the positions of two communication cores. The choice of parameters in each NoC depends on the characteristic of IPs in the same group in order to maximize communication adaptivity and performance. Results: Synthesis results show that the proposed multi-layer mesh topology NoC uses much less resources than the traditional NxM mesh topology NoC. Conclusion: This reduction in term of resources is assured by the considerable reduction in the length and number of global interconnects, resulting in an increase in the performance and decrease in the power consumption and area of wire limited circuits.

scholarly journals Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture

2019 ◽  
Vol 14 (2) ◽  
pp. 802
Author(s):  
Ng Yen Phing ◽  
M.N.Mohd Warip ◽  
Phaklen Ehkan ◽  
R Badlishah Ahmad ◽  
F.W. Zulkefli
Keyword(s):  
Power Consumption ◽  
Small Area ◽  
Network On Chip ◽  
Low Power Consumption ◽  
Cross Link ◽  
Ring Topology ◽  
Mesh Topology ◽  
Average Area ◽  
On Chip ◽  
Point To Point

<span>The size of the transistor has reached physical processor limitation in particular for traditional bus-based and point-to-point architecture in system-on-chip (SoC). Therefore, network-on-chip (NoC) was proposed as a solution. The performances required for the optimization of the NoC are low network latency, low power consumption, small area, and high throughput. However, recently the size of the NoC architecture has increased and the communication between cores to core become complicated. To overcome this disadvantages, topology plays an important role. In this paper, we reduce the number of the router in the 16 cores and 64 cores ring and mesh topologies by connected more numbers of node in each router. Result shows that reducing the number of the router in 64 cores ring topology outperforms the conventional topologies in term of area, power consumption, latency, and accepted packet rate. Reducing router in 64 cores ring topology decrease the average area, power consumption, latency, and increase the average accepted packet rate by 160.45%, 23.88%, 54.76%, and 223.88% over the 64 cores mesh, reducing router in mesh, ring, and cross-link mesh topologies.</span>

scholarly journals Bubble NoC – A Low Energy Network-on-Chip with Small Footprint and High Performance

2021 ◽  
Author(s):  
Gunnar Carlstedt ◽  
Mats Rimborg
Keyword(s):  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Transmission Gates ◽  
One Step ◽  
Small Footprint ◽  
On Chip ◽  
Local Connection ◽  
Bidirectional Transmission ◽  
Energy Network

<div>The Bubble NoC is based on simplicity and provides outstanding performance. Flow control is implemented by <i>bubbles</i>, which are inserted between the flits. The logic resembles a traffic situation where a vehicle only moves if the next position is empty. When a flit moves, a bubble is created behind it, and when there is a blocking the bubbles are collapsed as the flits behind are packed together. Even when the Bubble NoC is saturated, it degrades gracefully, and the execution continues.</div><div> Deterministic prerouting is used, with the address stored as markers in a 2 out of 32 code. The routing algorithm shifts the address one step at each hop and turns or finishes when a marker starts the address.</div><div> The physical implementation is a mesh of <i>streets</i> containing duplex links of 38 wires carrying 32-bit payload. Signaling is based on current injection that charges the wires. A switch is placed in a four-way crossing, with a fifth local connection into a street. The switch contains input registers for each approaching street. Straight through traffic is simply passed on, and a diagonal gate is used for turning traffic.</div><div> All switches are bidirectional transmission gates, and the control is distributed as a sidewalk in a few µm of the periphery surrounding the intersection. In a 14 nm technology, the streets are 8 μm wide, the crossing is 17 μm in square, the hop frequency 6.67 GHz and the energy for a datapath 4.1 fJ/bit/hop (150 µm).</div>

scholarly journals Applying Genetic Algorithm to Solve Partitioning and Mapping Problem for Mesh Network-on-Chip Systems

2021 ◽  
Vol 13 (1) ◽  
pp. 33-47
Author(s):  
Walid Mokthar Salh ◽  
Azeddien M. Sllame
Keyword(s):  
Genetic Algorithm ◽  
Power Consumption ◽  
Design Process ◽  
Network On Chip ◽  
Experimental Results ◽  
Mesh Network ◽  
Data Dependencies ◽  
Mapping Problem ◽  
Mesh Topology ◽  
On Chip

This paper presents a genetic based approach to the partitioning and mapping of multicore SoC cores over a NoC system that uses mesh topology. The proposed algorithm performs the partitioning and mapping by reducing communication cost and minimizing power consumption by placing those intercommunicated cores as close as possible together. A program developed in C++ in which the provided specification of the multicore MPSoC system captures all data dependencies before any start of the design process. Experimental results of several multimedia benchmarks demonstrates that the genetic-based approach able to find different satisfied implementations to the problem of partitioning and mapping of MPSoC cores over mesh-based NoC system that satisfies design goals.

YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs

2019 ◽  
Vol 28 (12) ◽  
pp. 1950202 ◽  
Author(s):  
Khyamling Parane ◽  
B. M. Prabhu Prasad ◽  
Basavaraj Talawar
Keyword(s):  
Design Space Exploration ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Tree Topology ◽  
Traffic Pattern ◽  
Mesh Topology ◽  
On Chip ◽  
Congestion Aware

Many-core systems employ the Network on Chip (NoC) as the underlying communication architecture. To achieve an optimized design for an application under consideration, there is a need for fast and flexible NoC simulator. This paper presents an FPGA-based NoC simulation acceleration framework supporting design space exploration of standard and custom NoC topologies considering a full set of microarchitectural parameters. The framework is capable of designing custom routing algorithms, various traffic patterns such as uniform random, transpose, bit complement and random permutation are supported. For conventional NoCs, the standard minimal routing algorithms are supported. For designing the custom topologies, the table-based routing has been implemented. A custom topology called diagonal mesh has been evaluated using table-based and novel shortest path routing algorithm. A congestion-aware adaptive routing has been proposed to route the packets along the minimally congested path. The congestion-aware adaptive routing algorithm has negligible FPGA area overhead compared to the conventional XY routing. Employing the congestion-aware adaptive routing, network latency is reduced by 55% compared to the XY routing algorithm. The microarchitectural parameters such as buffer depth, traffic pattern and flit width have been varied to observe the effect on NoC behavior. For the [Formula: see text] mesh topology, the LUT and FF usages will be increased from 32.23% to 34.45% and from 12.62% to 15% considering the buffer depth of 4 and flit widths of 16 bits, and 32 bits, respectively. Similar behavior has been observed for other configurations of buffer depth and flit width. The torus topology consumes 24% more resources than the mesh topology. The 56-node fat tree topology consumes 27% and 2.2% more FPGA resources than the [Formula: see text] mesh and torus topologies. The 56-node fat tree topology with buffer depth of 8 and 16 flits saturates at the injection rates of 40% and 45%, respectively.

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