scholarly journals Binary to RNS encoder for the moduli set {2n-1, 2n, 2n+1} with embedded diminished-1 channel for DSP application

2016 ◽  
Vol 29 (1) ◽  
pp. 101-112
Author(s):  
Ivan Krstic ◽  
Negovan Stamenkovic ◽  
Vidosav Stojanovic
Keyword(s):  
Dynamic Range ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
The Other ◽  
Minimal Amount ◽  
Residue Number ◽  
Fpga Chip ◽  
The One ◽  
Xilinx Fpga

A binary-to-residues encoder (forward encoder) is an essential building block for the residue number system digital signal processing (RNS DSP) and as such it should be built with a minimal amount of hardware and be efficient in terms of speed and power. The main parts of the forward encoder are residue generators which are usually classified into two categories: the one based on arbitrary moduli-set which make use of look-up tables, and the other based on the special moduli sets. A new memory less architecture of binary-to-RNS encoder based on the special moduli set {2n?1,2n,2n+1} with embedded modulo 2n+1 channel in the diminished-1 representation is presented. Any of two channels (standard modulo 2n +1, or modulo 2n+1 in the diminished-1 representation) operation can be performed by using a single switch. The proposed encoder has been implemented on a Xilinx FPGA chip for the various dynamic range requirements.

scholarly journals A Fault Tolerant Scheme for Detecting Overflow in Residue Number Microprocessors

2018 ◽  
Vol 7 (02) ◽  
pp. 23578-23587
Author(s):  
Agbedemnab P. A. ◽  
Agebure M. A. ◽  
Akobre S.
Keyword(s):  
Dynamic Range ◽  
Fault Tolerant ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
General Purpose ◽  
Correction Scheme ◽  
Residue Number ◽  
Efficient Scheme ◽  
General Purpose Computer

The decomposition of larger numbers into smaller ones termed as residues is the main operation behind the concept of Residue Number System (RNS); it possesses inherent features such as parallelism and independent digit arithmetic computations. These features of the RNS has made it desirable for applications that require intensive computations such as Digital Signal Processing (DSP), Digital Filtering and Convolutions. Overflow detection is one of the major challenges that confront the efficient implementation of RNS in general purpose computer processors. Overflow occurs in RNS when an illegitimate value is represented within legitimate range – Dynamic Range (DR) as if it is legitimate value. This misrepresentation of results, which usually arises during addition operations ultimately affects systems built on this Number System. It is therefore imperative that steps are taken not to only detect but correct the occurrence of overflow whenever it occurs. In this paper, an additive overflow detection and correction scheme for the moduli set  is presented. The scheme uses a redundant modulus to extend the DR of the moduli set. The proposed scheme is demonstrated theoretically to be an efficient scheme by comparing it to previous similar works.

LARGE DYNAMIC RANGE RNS SYSTEMS AND THEIR RESIDUE TO BINARY CONVERTERS

2007 ◽  
Vol 16 (02) ◽  
pp. 267-286 ◽  
Author(s):  
ALEXANDER SKAVANTZOS ◽  
MOHAMMAD ABDALLAH ◽  
THANOS STOURAITIS
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Chinese Remainder Theorem ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
New Class ◽  
Mixed Radix Conversion ◽  
Residue Number ◽  
Signal Processors

The Residue Number System (RNS) is an integer system appropriate for implementing fast digital signal processors. It can be used for supporting high-speed arithmetic by operating in parallel channels without need for exchanging information among the channels. In this paper, two novel RNS are proposed. First, a new RNS system based on the modulus set {2n+1, 2n - 1, 2n + 1, 2n + 2(n+1)/2 + 1, 2n - 2(n+1)/2 + 1}, n odd, is developed, along with an efficient implementation of its residue-to-weighted converter. The new RNS is a balanced five-modulus system, appropriate for large dynamic ranges. The proposed residue-to-binary converter is fast and hardware efficient and is based on a one's complement multi-operand adder that adds operands of size only 80% of the size dictated by the system's dynamic range. Second, a new class of multi-modulus RNS systems is proposed. These systems are based on sets consisting of two groups of moduli with the modulus product within one group being of the form 2a(2b - 1), while the modulus product within the other group is of the form 2c - 1. Their RNS-to-weighted converters are based on efficient combinations of the Chinese Remainder Theorem and Mixed Radix Conversion decoding techniques. Systems based on four, five, and seven moduli are constructed and analyzed. The new systems allow efficient implementations for their RNS-to-weighted decoders, imply fast and balanced RNS arithmetic, and may achieve large dynamic ranges. The presented residue-to-weighted converters for these systems rely on simple mod (2x - 1) hardware, which can be easily implemented as one's complement hardware.

Perspective and Opportunities of Modulo 2n−1 Multipliers in Residue Number System: A Review

2020 ◽  
Vol 29 (11) ◽  
pp. 2030008
Author(s):  
Raj Kumar ◽  
Ritesh Kumar Jaiswal ◽  
Ram Awadh Mishra
Keyword(s):  
Word Length ◽  
Dynamic Range ◽  
High Dynamic Range ◽  
Number System ◽  
Residue Number System ◽  
System A ◽  
Essential Components ◽  
Residue Number ◽  
Speed Up ◽  
Computational Circuits

Modulo multiplier has been attracting considerable attention as one of the essential components of residue number system (RNS)-based computational circuits. This paper contributes a comprehensive review in the design of modulo [Formula: see text] multipliers for the first time. The modulo multipliers can be implemented using ROM (look-up-table) as well as VLSI components (memoryless); however, the former is preferable for lower word-length and later for larger word-length. The modular and parallelism properties of RNS are used to improve the performance of memoryless multipliers. Moreover, a Booth-encoding algorithm is used to speed-up the multipliers. Also, an advanced modulo [Formula: see text] multiplier based on redundant RNS (RRNS) could be further chosen for very high dynamic range. These perspectives of modulo [Formula: see text] multipliers have been extensively studied for recent state-of-the-art and analyzed using Synopsis design compiler tool.

scholarly journals Revisiting Sum of Residues Modular Multiplication

2010 ◽  
Vol 2010 ◽  
pp. 1-9 ◽  
Author(s):  
Yinan Kong ◽  
Braden Phillips
Keyword(s):  
Public Key Cryptography ◽  
Number System ◽  
Residue Number System ◽  
The Other ◽  
Public Key ◽  
Modular Multiplication ◽  
Residue Number ◽  
The Cost

In the 1980s, when the introduction of public key cryptography spurred interest in modular multiplication, many implementations performed modular multiplication using a sum of residues. As the field matured, sum of residues modular multiplication lost favor to the extent that all recent surveys have either overlooked it or incorporated it within a larger class of reduction algorithms. In this paper, we present a new taxonomy of modular multiplication algorithms. We include sum of residues as one of four classes and argue why it should be considered different to the other, now more common, algorithms. We then apply techniques developed for other algorithms to reinvigorate sum of residues modular multiplication. We compare FPGA implementations of modular multiplication up to 24 bits wide. The sum of residues multipliers demonstrate reduced latency at nearly 50% compared to Montgomery architectures at the cost of nearly doubled circuit area. The new multipliers are useful for systems based on the Residue Number System (RNS).

A MEMORYLESS REVERSE CONVERTER FOR THE 4-MODULI SUPERSET {2n - 1, 2n, 2n + 1, 2n + 1 - 1}

2000 ◽  
Vol 10 (01n02) ◽  
pp. 85-99 ◽  
Author(s):  
A. P VINOD ◽  
A. BENJAMIN PREMKUMAR
Keyword(s):  
High Performance ◽  
Dynamic Range ◽  
Number System ◽  
Residue Number System ◽  
Main Challenge ◽  
Reverse Converter ◽  
Residue Number ◽  
Compensation Technique ◽  
The Common ◽  
Performance Computing

This paper presents a residue number system to binary converter in the four moduli set {2n - 1, 2n, 2n + 1, 2n + 1 - 1}, valid for even values of n. This moduli set is an extension of the popular set {2n - 1, 2n + 1}. The number theoretic properties of the moduli set of the form 2n ± 1 are exploited to design the converter. The main challenge of dealing with fractions in Residue Number System is overcome by using the fraction compensation technique. A hardware implementation using only adders is also proposed. When compared to the common three moduli reverse converters, this four moduli converter offers a larger dynamic range and higher parallelism, which makes it useful for high performance computing.

MULTIFUNCTION RNS MODULO 2n ± 1 MULTIPLIERS

2012 ◽  
Vol 21 (04) ◽  
pp. 1250027 ◽  
Author(s):  
TSO-BING JUANG ◽  
CHAO-TSUNG KUO ◽  
GO-LONG WU ◽  
JIAN-HAO HUANG
Keyword(s):  
Real Time ◽  
Number System ◽  
Residue Number System ◽  
Real Time Processing ◽  
Time Processing ◽  
The Real ◽  
Delay Constraints ◽  
Residue Number ◽  
The One

In this paper, multifunction residue number system (RNS) modulo (2n ± 1) multipliers are proposed. By adopting common circuits for summing up the partial products with extra controls, our proposed multipliers could perform both modulo (2n + 1) and (2n - 1) multiplications. The levels for summation of partial products are n + 1, which are same as the conventional modulo multipliers which with only one kind of modulo multiplications. The proposed multifunction modulo (2n ± 1) multipliers can save at least about 42.5% area under the same delay constraints and above 65.8% Area × Delay Product (ADP) compared with the one composed of modulo (2n + 1) and modulo (2n - 1) multiplication operations. Our proposed multipliers could be applied to ease the tremendous computation overload in the real-time processing applications.

Improved Lempel-Ziv-Welch’s Error Detection and Correction Scheme using Redundant Residue Number System (RRNS)

2017 ◽  
Vol 2 (6) ◽  
pp. 25-30 ◽  
Author(s):  
Alhassan Abdul- Barik ◽  
Mohammed Ibrahim Daabo ◽  
Stephen Akobre
Keyword(s):  
Error Detection ◽  
Dynamic Range ◽  
Number System ◽  
Residue Number System ◽  
Compression Scheme ◽  
Encrypted Data ◽  
Correction Scheme ◽  
Error Detection And Correction ◽  
Residue Number ◽  
Redundant Residue Number System

The greatest difficulty of compressing data is the assurance of the security, integrity, and accuracy of the data in storage in volatile media or transmission in network communication channels. Various methods have been proposed for dealing with the accuracy and consistency of compressed and encrypted data using error detection and correction mechanisms. The Redundant Residue Number System (RRNS) which is a trait of Residue Number System (RNS) is one of the available methods for detecting and correcting errors which involves the addition of extra moduli called redundant moduli. In this paper, Residue Number System (RNS) is efficiently applied to the Lempel-Ziv-Welch (LZW) compression algorithm resulting in new LZW-RNS compression scheme using the traditional moduli set, and two redundant moduli added resulting in the moduli set {2^n-1,〖 2〗^n,〖 2〗^n+1,〖 2〗^2n-3,〖 2〗^2n+1} for the purposes of error detection and correction. This is done by constraining the data or information within the legitimate range of the dynamic range provided by the non-redundant moduli. Simulation with MatLab shows the efficiency and fault tolerance of the proposed scheme than the traditional LZW compression method and other related known state of the art schemes.

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